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Intel Internal Foundry Model Webinar

Intel Internal Foundry Model Webinar
by Scotten Jones on 06-21-2023 at 12:00 pm

IAO Investor Webinar Slides to post on our INTC website PDF Page 07

Intel held a webinar today to discuss their IDM2.0 internal foundry model. On the call were Dave Zinsner Executive Vice President and Chief Financial Officer and Jason Grebe Corporate Vice President and General Manager of the Corporate Planning Group.

On a humorous note, the person moderating the attendee questions sounded … Read More


The Updated Legacy of Intel CEOs

The Updated Legacy of Intel CEOs
by Daniel Nenni on 06-21-2023 at 10:00 am

Intel HQ 2023

(First published December 24, 2014)

A list of the best and worst CEOs in 2014 was recently published. The good news is that none of our semiconductor CEOs were on the worst list. The bad news is that none of our semiconductor CEOs were on the best list either. I will be writing about the CEOs that made our industry what it is today starting… Read More


Synopsys Expands Agreement with Samsung Foundry to Increase IP Footprint

Synopsys Expands Agreement with Samsung Foundry to Increase IP Footprint
by Kalar Rajendiran on 06-20-2023 at 6:00 am

Synopsys Samsung silicon wafer

Many credible market analysis firms are predicting the semiconductor market to reach the trillion dollar mark over the next six years or so. Just compare this to the more than six decades it took for the market to cross the $500 billion mark. The projected growth rate is incredible indeed and is driven by fast growing market segments… Read More


Keynote Sneak Peek: Ansys CEO Ajei Gopal at Samsung SAFE Forum 2023

Keynote Sneak Peek: Ansys CEO Ajei Gopal at Samsung SAFE Forum 2023
by Daniel Nenni on 06-19-2023 at 10:00 am

Image

As one of the world’s leading chip foundries, Samsung occupies a vital position in the semiconductor value chain. The annual Samsung Advanced Foundry Ecosystem (SAFE™) Forum is a must-go event for semiconductor and electronic design automation (EDA) professionals. Ajei Gopal, President and CEO of Ansys, has the honor of delivering… Read More


TSMC Doubles Down on Semiconductor Packaging!

TSMC Doubles Down on Semiconductor Packaging!
by Daniel Nenni on 06-14-2023 at 6:00 am

TSMC 3DFabric Integration

Last week TSMC announced the opening of an advanced backend fab for the expansion of the TSMC 3DFabric System Integration Technology. It’s a significant announcement as the chip packaging arms race with Intel and Samsung is heating up.

Fab 6 is TSMC’s first all-in-one advanced packaging and testing fab which is part of the… Read More


VLSI Symposium – Intel PowerVia Technology

VLSI Symposium – Intel PowerVia Technology
by Scotten Jones on 06-12-2023 at 6:00 am

Slide4

At the 2023 VLSI Symposium on Technology and Circuits, Intel presented two papers on their PowerVia technology. We received a pre-conference briefing on the technology embargoed until the conference began and received the papers.

Traditionally all interconnects have taken place on the front side of devices with signal and … Read More


TSMC Clarified CAPEX and Revenue for 2023!

TSMC Clarified CAPEX and Revenue for 2023!
by Daniel Nenni on 06-06-2023 at 2:00 pm

TSMC HQ Taiwan

TSMC clarified CAPEX and revenue for 2023 last night at the Annual Shareholders Meeting. Last year TSMC guided up during this meeting but this year they guided down. CAPEX was guided down to the lower end of $36B-$32B.  Revenue was guided down from low-single to mid-single digit so maybe down another percent or two. The TSMC Jan… Read More


Investing in a sustainable semiconductor future: Materials Matter

Investing in a sustainable semiconductor future: Materials Matter
by Daniel Nenni on 05-31-2023 at 6:00 am

EMD LinkedIn Twitter Materials Matter

In 2020 TSMC established its Net Zero Project with a goal of net zero emissions by 2050. I remember wondering how could this possibly be done before 2050 or at all for that matter. After working with TSMC for 20+ years I have learned never to bet against them on any topic and green manufacturing is one of them, absolutely.

TSMC presented… Read More


Chiplet Interconnect Challenges and Standards

Chiplet Interconnect Challenges and Standards
by Daniel Payne on 05-25-2023 at 10:00 am

Multi die IP min

For decades now I’ve watched the incredible growth of SoCs in terms of die size, transistor count, frequency and complexity. Instead of placing all of the system complexity into a single, monolithic chip, there are now compelling reasons to use a multi-chip approach, like when the maximum die size limit is reached, or it’s… Read More


Alphawave Semi Showcases 3nm Connectivity Solutions and Chiplet-Enabled Platforms for High Performance Data Center Applications

Alphawave Semi Showcases 3nm Connectivity Solutions and Chiplet-Enabled Platforms for High Performance Data Center Applications
by Daniel Nenni on 05-04-2023 at 6:00 am

Alphawave Semi 3nm Eye Diagram

There were quite a few announcements at the TSMC Technical Symposium last week but the most important, in my opinion, were based on TSMC N3 tape-outs. Not only is N3 the leading 3nm process it is the only one in mass production which is why all of the top tier semiconductor companies are using it. TSMC N3 will be the most successful node… Read More