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Moore’s Law and Semiconductor Design and Manufacturing

Moore’s Law and Semiconductor Design and Manufacturing
by Daniel Nenni on 03-12-2011 at 4:51 am

The semiconductor design and manufacturing challenges at 40nm and 28nm are a direct result ofMoore’s Law, the climbing transistor count and shrinking geometries. It’s a process AND design issue and the interaction is at the transistor level. Transistors may be shrinking, but atoms aren’t. So now it actually matters when even… Read More


TSMC 2011 Technology Symposium Theme Explained

TSMC 2011 Technology Symposium Theme Explained
by Daniel Nenni on 03-09-2011 at 6:49 pm

The 17[SUP]th[/SUP] Annual TSMC Technology Symposium will be held in San Jose California on April 5[SUP]th[/SUP], 2011. Dr. Morris Chang will again be the keynote speaker. The theme this year is “Trusted Technology and Capacity Provider”and I think it’s important to not only hear what people are saying but also understand why… Read More


Semiconductor Power Crisis and TSMC!

Semiconductor Power Crisis and TSMC!
by Daniel Nenni on 03-02-2011 at 8:48 pm

Power grids all over the world are already overloaded even without the slew of new electronic gadgets and cars coming out this year. At ISSCC, Dr. Jack Sun, TSMC Vice President of R&D and Chief Technology Officer made the comparison of a human brain to the closest thing available in silicon, a graphical processing unit (GPU).… Read More


Intel Sandy Bridge Fiasco and EDA

Intel Sandy Bridge Fiasco and EDA
by Daniel Nenni on 02-27-2011 at 6:49 am

I purchased two Toyotas last year and both have since been recalled. Why has Toyota spent $1B+ on recalls in recent years? Same reason why it will cost Intel $700M (which does not include reputation damage) to recall Sandy Bridge chip sets, because someone did not do their job! The WHAT has been discussed, lets talk about HOW it happened.… Read More


Custom and AMS Design

Custom and AMS Design
by Daniel Payne on 02-21-2011 at 10:06 pm

Samsung%203DIC%20Roadmap

For IC designers creating full-custom or AMS designs there are plenty of challenges to getting designs done right on the first spin of silicon. Let me give you a sneak peek into what’s being discussed at the EDA Tech Forum in Santa Clara, CA on March 10th that will be of special interest to you:

3D TSV (Through Silicon Vias) are… Read More


DRC+, DFM, CMP, Variablility

DRC+, DFM, CMP, Variablility
by Daniel Payne on 02-10-2011 at 12:42 pm

When I worked at Intel as a circuit design engineer I could talk directly with the technology development engineers to understand how to really push my DRAM designs and get the smallest possible memory cell layout that would still yield well, provide fast access time, and long refresh cycles.

(United States Patent 6661699. Inventor:… Read More


TSMC Raises The Semiconductor Bar With 450mm!

TSMC Raises The Semiconductor Bar With 450mm!
by Daniel Nenni on 02-03-2011 at 2:34 pm

During the most recent conference call (transcript), TSMC not only beat revised estimates and announced record spending levels for 2011, Morris Chang also officially announced that a 450mm fab (Fab 12 Phase VI) is currently in the planning stages with target production @ 20nm in 2015. This is HUGE!

According to Morris Chang:

“FRead More


TSMC Versus The FabClub!

TSMC Versus The FabClub!
by Daniel Nenni on 01-23-2011 at 11:00 pm


The Common Platform Technology Forum last week was not well attended, less than half than the GlobalFoundries Conference. It was deja vu of previous CP forums but there were a couple of surprises to go with the disappointment. The lunch line was long, but fortunately I was escorted to the press lunch featuring VIP’s from Samsung,… Read More


CES GlobalFoundries Party ( pics )

CES GlobalFoundries Party ( pics )
by Daniel Nenni on 01-11-2011 at 1:13 am

Unlike the last CES, this year I saw compelling technology, technology that will definitely drive the semiconductor industry and make the analyst fortunetellers look bad yet again. Anyone who thinks semiconductor growth next year will be in single digits is absolutely wrong, TSMC will grow even more, 20%+. First and foremost… Read More


The Future of Semiconductor Design!

The Future of Semiconductor Design!
by Daniel Nenni on 12-26-2010 at 10:15 pm

Is EDA still an appropriate term for what we do? What applications will drive future semiconductor design innovation? Will further consolidation be required for EDA to thrive again? They are all good questions, questions that will hopefully be properly addressed at the EDAC CEO Forecast and Industry Vision event next week but… Read More