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Lithography Resolution Limits – Arrayed Features

Lithography Resolution Limits – Arrayed Features
by Fred Chen on 04-17-2020 at 6:00 am

Lithography Resolution Limits Arrayed Features

State-of-the-art chips will always include some portions which are memory arrays, which also happen to be the densest portions of the chip. Arrayed features are the main targets for lithography evaluation, as the feature pitch is well-defined, and is directly linked to the cost scaling (more features per wafer) from generation… Read More


Lithography Resolution Limits: Paired Features

Lithography Resolution Limits: Paired Features
by Fred Chen on 04-07-2020 at 10:00 am

Lithography Resolution Limits Paired Features

As any semiconductor process advances to the next generation or “node”, a sticky point is how to achieve the required higher resolution. As noted in another article [1], multipatterning (the required use of repeated patterning steps for a particular feature) has been practiced already for many years, and many have… Read More


Low Energy Electrons Set the Limits for EUV Lithography

Low Energy Electrons Set the Limits for EUV Lithography
by Fred Chen on 03-25-2020 at 6:00 am

Low Energy Electrons Set the Limits for EUV Lithography

EUV lithography is widely perceived to be the obvious choice to replace DUV lithography due to the shorter wavelength(s) used. However, there’s a devil in the details, or a catch if you will.

Electrons have the last word
The resist exposure is completed by the release of electrons following the absorption of the EUV photon.… Read More


The Need for Low Pupil Fill in EUV Lithography

The Need for Low Pupil Fill in EUV Lithography
by Fred Chen on 03-15-2020 at 10:00 am

The Need for Low Pupil Fill in EUV Lithography 1

Extreme ultraviolet (EUV) lithography targets sub-20 nm resolution using a wavelength range of ~13.3-13.7 nm (with some light including DUV outside this band as well) and a reflective ring-field optics system. ASML has been refining the EUV tool platform, starting with the NXE:3300B, the very first platform with a numerical

Read More

SPIE 2020 – Applied Materials Material-Enabled Patterning

SPIE 2020 – Applied Materials Material-Enabled Patterning
by Scotten Jones on 03-13-2020 at 10:00 am

2020 SPIE Media Briefing Full Slides for Scott Jones Page 16

I wasn’t able to attend the SPIE Advanced Lithography Conference this year for personal reasons, but Applied Materials was kind enough to set up a phone briefing for me with Regina Freed to discuss their Materials-Enabled Patterning announcement.

At IEDM Applied Materials (AMAT) tried to put together a panel across the entire… Read More


A Forbidden Pitch Combination at Advanced Lithography Nodes

A Forbidden Pitch Combination at Advanced Lithography Nodes
by Fred Chen on 03-06-2020 at 10:00 am

A Forbidden Pitch Combination at Advanced Lithography Nodes

The current leading edge of advanced lithography nodes (e.g., “7nm” or “1Z nm”) features pitches (center-center distances between lines) in the range of 30-40 nm. Whether EUV (13.5 nm wavelength) or ArF (193 nm wavelength) lithography is used, one thing for certain is that the minimum imaged pitch … Read More


LithoVision – Economics in the 3D Era

LithoVision – Economics in the 3D Era
by Scotten Jones on 03-04-2020 at 6:00 am

Slide3

Each year on the Sunday before the SPIE Advanced Lithography Conference, Nikon holds their LithoVision event. This year I had the privilege of being invited to speak for the third consecutive year, unfortunately, the event had to be canceled due to concerns over the COVID-19 virus but by the time the event was canceled I had already… Read More


Coronavirus Chops SPIE Litho EUV Conference

Coronavirus Chops SPIE Litho EUV Conference
by Robert Maire on 03-01-2020 at 6:00 am

SPIE EUV 2020 Coronavirus

Corona Curtails already quiet SPIE Litho conference
Our best guess is that attendance was off by 30% from last years SPIE conference due to a lack of travelers from many Asian areas obviously out of Corona fear. Even Intel, which is a few miles away was a virtual no-show with a mass cancellation.

More importantly, virtually all after… Read More


ASML “A Swing to Memory Looms” Nice performance while awaiting Memory bounce

ASML “A Swing to Memory Looms” Nice performance while awaiting Memory bounce
by Robert Maire on 01-24-2020 at 6:00 am

ASML 2020 Logic Memory
  • Good Q4 & 2019 despite weak memory
  • 2020 will be up year but memory an unknown
  • EUV ramp is on track – no China or memory impact
ASML reports an “in line” Q4 despite industry weak 2019

ASML reported sales of 4B Euros and a nice gross margin of 48% resulting in 2.70 Euros per share in earnings.  Orders came in at 2.4B

Read More

IEDM 2019 – Imec Interviews

IEDM 2019 – Imec Interviews
by Scotten Jones on 01-21-2020 at 6:00 am

Slide4

Imec is one of the premier semiconductor research organizations and at IEDM they presented dozens of papers. I had the opportunity to see several of the papers presented and interview 3 of Imec’s researchers.

Jan Van Houdt, DMTS ferroelectric and exploratory memory

I have had very interesting discussions with Imec researchers… Read More