Tuple Banner
WP_Term Object
(
    [term_id] => 16126
    [name] => Lithography
    [slug] => lithography
    [term_group] => 0
    [term_taxonomy_id] => 16126
    [taxonomy] => category
    [description] => 
    [parent] => 0
    [count] => 195
    [filter] => raw
    [cat_ID] => 16126
    [category_count] => 195
    [category_description] => 
    [cat_name] => Lithography
    [category_nicename] => lithography
    [category_parent] => 0
    [is_post] => 
)

Five Billion Pulses Later: What DUV Optics Testing Reveals About Semiconductor Tool Uptime

Five Billion Pulses Later: What DUV Optics Testing Reveals About Semiconductor Tool Uptime
by Admin on 08-30-2026 at 12:00 pm

umberto jXd2FSvcRr8 unsplash (2)

By Dr. Sabina Kuprėnaitė

Deep-ultraviolet optics used in semiconductor lithography may be exposed to billions of pulses over their service life. That creates a qualification challenge that initial reflectance specifications or laser-induced damage thresholds alone cannot answer.

A mirror may meet its optical specification… Read More


Huawei Can’t Shrink Its Chips, So It’s Folding Them

Huawei Can’t Shrink Its Chips, So It’s Folding Them
by Daniel Nenni on 08-27-2026 at 8:00 am

Huawei Can’t Shrink Its Chips, So It’s Folding Them

On May 25, Huawei semiconductor chief He Tingbo unveiled LogicFolding, an architecture intended to advance chip performance without relying on ever-smaller transistors. Presented alongside Huawei’s “Tau Scaling Law,” the approach prioritizes signal speed over transistor dimensions. It is a genuine engineering response… Read More


Reducing EUV Exposure Dose Through Underlayer Engineering

Reducing EUV Exposure Dose Through Underlayer Engineering
by Admin on 08-20-2026 at 2:00 pm

Reducing EUV Exposure Dose Through Underlayer Engineering

Extreme-ultraviolet lithography is essential for manufacturing advanced semiconductor devices, but its continued scaling presents a difficult materials problem. Photoresists must simultaneously provide high resolution, low exposure dose, limited line-edge or linewidth roughness, and extremely low defectivity. … Read More


ASML’s Path to Lithography Dominance—and the Coming Maskless Revolution

ASML’s Path to Lithography Dominance—and the Coming Maskless Revolution
by Daniel Nenni on 08-14-2026 at 6:00 am

ASML’s Path to Lithography Dominance—and the Coming Maskless Revolution

ASML’s dominance was not born from a single invention. It emerged from four decades of systems engineering, supplier orchestration, and repeated bets on lithographic transitions that competitors judged too expensive. Founded in 1984 as a Philips–ASM joint venture, the Dutch company first differentiated itself with modular… Read More


Intel and TSMC Take Different Paths to High-NA EUV

Intel and TSMC Take Different Paths to High-NA EUV
by Daniel Nenni on 08-07-2026 at 8:00 am

Intel TSMC HNA EUV 2026

Intel and TSMC are pursuing the same objective—manufacturing smaller, faster, and more energy-efficient semiconductors—but they have adopted different strategies for advanced lithography. Intel moved early to develop High-Numerical-Aperture Extreme Ultraviolet lithography, commonly called High-NA EUV, while TSMC… Read More


CEO Interview with Yossi Meyouhas of Xsight Labs

CEO Interview with Yossi Meyouhas of Xsight Labs
by Daniel Nenni on 06-25-2026 at 2:00 pm

Yossi meyouhas

Yossi Meyouhas is the CEO of Xsight Labs. Yossi joined Xsight Labs in May 2021 as Chief Operating Officer. Prior to Xsight Labs, Yossi was SVP R&D in Valens Semiconductors (2017-2021), and before that served in multiple senior positions in Marvell Technology Group, the last being SVP Engineering and General Manager of Marvell

Read More

ASML High-NA EUV is Not Ready for High-Volume Production

ASML High-NA EUV is Not Ready for High-Volume Production
by Daniel Nenni on 05-22-2026 at 8:00 am

ASML Elephant High NA EUV

Contrary to the popular press, ASML High-NA EUV is not ready for logic production yet—and it may never be, at least not in the form originally envisioned. If you remember how long it took conventional EUV to become production-worthy—arguably 5–10 years—this should not come as a surprise. More importantly, this is no longer just… Read More


Crossing the Yield Cliff: IDP V6 and the Future of Manufacturing Forecasting

Crossing the Yield Cliff: IDP V6 and the Future of Manufacturing Forecasting
by Admin on 05-18-2026 at 10:00 am

Crossing the Yield Cliff IDP V6 and the Future of Manufacturing Forecasting

The paper, Industrial Defectivity Prediction (IDP) V6: A Two-Layer Yield Cliff Framework for Cross-Industry Mass-Production Forecasting, presents a generalized industrial yield-modeling architecture that extends the classical Negative Binomial framework through a two-layer phenomenological structure designed … Read More


Chemical Origins of Environmental Modifications to MOR Lithographic Chemistry

Chemical Origins of Environmental Modifications to MOR Lithographic Chemistry
by Daniel Nenni on 03-25-2026 at 10:00 am

Chemical Origins of Environmental Modifications to MOR Lithographic Chemistry

In the pursuit of advanced extreme ultraviolet (EUV) lithography for high-NA patterning, metal oxide resists (MORs) offer significant promise but face challenges like critical dimension (CD) variation due to atmospheric interactions. Presented at SPIE Advanced Lithography + Patterning 2025 by Kevin M. Dorney and colleagues… Read More


Beyond Moore’s Law: High NA EUV Lithography Redefines Advanced Chip Manufacturing

Beyond Moore’s Law: High NA EUV Lithography Redefines Advanced Chip Manufacturing
by Daniel Nenni on 03-23-2026 at 8:00 am

DSC00975

The imec installation of the ASML EXE:5200 High Numerical Aperture (High NA) extreme ultraviolet (EUV) lithography system at imec represents a pivotal advancement in semiconductor manufacturing and research. This system, installed in imec’s 300 mm cleanroom in Leuven, Belgium, introduces unprecedented lithographic resolution… Read More