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(
    [term_id] => 16126
    [name] => Lithography
    [slug] => lithography
    [term_group] => 0
    [term_taxonomy_id] => 16126
    [taxonomy] => category
    [description] => 
    [parent] => 0
    [count] => 169
    [filter] => raw
    [cat_ID] => 16126
    [category_count] => 169
    [category_description] => 
    [cat_name] => Lithography
    [category_nicename] => lithography
    [category_parent] => 0
    [is_post] => 
)

Variable Cell Height Track Pitch Scaling Beyond Lithography

Variable Cell Height Track Pitch Scaling Beyond Lithography
by Fred Chen on 03-20-2025 at 6:00 am

Fred Chen Litho 1

Two approaches compared

With half-pitch approaching 10 nm, EUV patterning is heavily impacted by stochastic effects, which are aggravated from reduced image contrast from electron blur [1]. A two-mask (“LELE”: Litho-Etch-Litho-Etch) approach was proposed to pattern core features for self-aligned double patterning (SADP)… Read More


A Realistic Electron Blur Function Shape for EUV Resist Modeling

A Realistic Electron Blur Function Shape for EUV Resist Modeling
by Fred Chen on 03-13-2025 at 10:00 am

EUV Image 4

Peak probability at zero distance actually makes no sense

In lithography, it is often stated that the best resolution that can be achieved depends on wavelength and numerical aperture (NA), but this actually only applies to the so-called “aerial” image. When the image is actually formed in the resist layer, it also depends on an… Read More


Powering the Future: How Engineered Substrates and Material Innovation Drive the Semiconductor Revolution

Powering the Future: How Engineered Substrates and Material Innovation Drive the Semiconductor Revolution
by Kalar Rajendiran on 03-03-2025 at 6:00 am

Substrate Vision Summit Engineered Substrate Panel Session

Engineered substrate technology is driving an evolution within the semiconductor industry. As Moore’s Law reaches its limits, the focus is shifting from traditional planar wafer scaling to innovative material engineering and 3D integration. Companies like Soitec, Intel and Samsung are pioneering this transition, unlocking… Read More


Rethinking Multipatterning for 2nm Node

Rethinking Multipatterning for 2nm Node
by Fred Chen on 02-23-2025 at 10:00 am

https3A2F2Fsubstack post media.s3.amazonaws.com2Fpublic2Fimages2F4322f291 179c 4968 b59c 218f0cf0ab94 385x289

Whether EUV or DUV doesn’t matter at 20 nm pitch
The International Roadmap for Devices and Systems, 2022 Edition, indicates that the “2nm” node due in 2025 (this year) has a minimum (metal) half-pitch of 10 nm [1]. This is, in fact, less than the resolution of a current state-of-the-art EUV system, with a numerical aperture… Read More


Resist Loss Model for the EUV Stochastic Defectivity Cliffs

Resist Loss Model for the EUV Stochastic Defectivity Cliffs
by Fred Chen on 02-06-2025 at 10:00 am

Exposing EUV 1

The occurrences of notorious stochastic defects in EUV lithography have resulted in CD or corresponding dose windows with the lower and higher bounds being characterized as “cliffs” [1-3], since the defect density increases exponentially when approaching these bounds. The defects at lower doses have been attributed to the… Read More


Stochastic Effects Blur the Resolution Limit of EUV Lithography

Stochastic Effects Blur the Resolution Limit of EUV Lithography
by Fred Chen on 01-08-2025 at 6:00 am

Stochastic Effects Blur the Resolution Limit of EUV Lithography

Conventionally, the resolution limit of a lithography system with wavelength l and numerical aperture NA is given by half-pitch = 0.25 wavelength/NA. With the use of EUV lithography, however, electron blur needs to be added [1]. The impact of this blur is to reduce the contrast [2]. Blur reduces the modulation amplitude by a factor… Read More


Can LELE Multipatterning Help Against EUV Stochastics?

Can LELE Multipatterning Help Against EUV Stochastics?
by Fred Chen on 01-06-2025 at 6:00 am

Can LELE Multipatterning Help Against EUV Stochastics

Previously, I had indicated how detrimental stochastic effects at pitches below 50 nm should lead to reconsidering the practical resolution limit for EUV lithography [1]. This is no exaggeration, as stochastic effects have been observed for 24 nm half-pitch several years ago [2,3]. This then leads to the question of whether … Read More


Stochastic Pupil Fill in EUV Lithography

Stochastic Pupil Fill in EUV Lithography
by Fred Chen on 12-24-2024 at 6:00 am

Exposing EUV

Pupil fill tradeoff again

EUV lithography continues to be plagued by its stochastic nature.

This stochastic nature is most clearly portrayed by the random fluctuation of the absorbed photon number at a given location. For example, consider an absorbed dose of 10 mJ/cm2 amounts to 6.8 photons of energy 92 eV absorbed in a square … Read More


ASML surprise not a surprise (to us)- Bifurcation- Stocks reset- China headfake

ASML surprise not a surprise (to us)- Bifurcation- Stocks reset- China headfake
by Robert Maire on 10-16-2024 at 10:00 am

ASML 2024 Downturn
  • Investors finally realize the upcycle isn’t as strong as stocks indicated
  • Industry Bifurcation between AI & rest of industry continues
  • China spending risk/overhang finally kicks in
  • AI is super strong, majority of chips remain weak- Invest accordingly
ASML simply states chip industry reality that investors have
Read More

Application-Specific Lithography: Patterning 5nm 5.5-Track Metal by DUV

Application-Specific Lithography: Patterning 5nm 5.5-Track Metal by DUV
by Fred Chen on 08-08-2024 at 6:00 am

Application Specific Lithography I

At IEDM 2019, TSMC revealed two versions of 5nm standard cell layouts: a 5.5-track DUV-patterned version and a 6-track EUV-patterned version [1]. Although the metal pitches were not explicitly stated, later analyses of a 5nm product, namely, Apple’s A15 Bionic chip, revealed a cell height of 210 nm [2]. For the 6-track … Read More