In the march to more capable, faster, smaller, and lower power systems, Moore’s Law gave software a free ride for over 30 years or so purely on semiconductor process evolution. Compute hardware delivered improved performance/area/power metrics every year, allowing software to expand in complexity and deliver more capability… Read More
Semiconductor Intellectual Property
Mapping SysML to Hardware Architecture
The Systems Modeling Language (SysML) is used by systems engineers that want to specify, analyze, design, verify and validate a specific system. SysML started out as an open-source project, and it’s a subset of the Unified Modeling Language (UML). Mirabilis Design has a tool called VisualSim Architect that imports your… Read More
Securing Memory Interfaces
News of hackers breaking into systems is becoming common place these days. While many of the breaches reported to date may have been due to security flaws in software, vulnerabilities exist in hardware too. As a result, the topic of security is getting increased attention within the semiconductor industry around system-on-chip… Read More
Adaptive Clock Technology for Real-Time Droop Response
In integrated circuit terminology, a droop is the voltage drop that happens in a circuit. This is a well-known phenomenon and can happen due to the following reasons. The power supply falls below the operating range for which a chip was designed for, resulting in a droop. More current is drawn by the conductive elements than they … Read More
Scaling the RISC-V Verification Stack
The RISC-V open ISA premise was clearly a good bet. It’s taking off everywhere, however verification is still a challenge. As an alternative to Arm, the architecture and functionality from multiple IP providers looks very competitive, but how do RISC-V providers and users ensure the same level of confidence we have in Arm? Arm … Read More
JESD204D: Expert insights into what we Expect and how to Prepare for the upcoming Standard
Join our upcoming webinar on JESD204 and get insights into what we predict the upcoming JESD204D standard will contain, based on many years of experience working with JESD204.
Our expert speaker, Piotr Koziuk, has over a decade of experience with JESD204 standards and is a member of the JEDEC Standardization Committee. He will… Read More
MIPI D-PHY IP brings images on-chip for AI inference
Edge AI inference is getting more and more attention as demand grows for AI processing across an increasing number of diverse applications, including those requiring low-power chips in a wide range of consumer and enterprise-class devices. Much of the focus has been on optimizing the neural network processing engine for these… Read More
Deep thinking on compute-in-memory in AI inference
Neural network models are advancing rapidly and becoming more complex. Application developers using these new models need faster AI inference but typically can’t afford more power, space, or cooling. Researchers have put forth various strategies in efforts to wring out more performance from AI inference architectures,… Read More
DSP Innovation Promises to Boost Virtual RAN Efficiency
5G is already real, though some of us are wondering why our phone connections aren’t faster. That perspective misses the real intent of 5G – to extend high throughput (and low latency) communication to a vast number and variety of edge devices beyond our phones. One notable application is Fixed Wireless Access (FWA), promising … Read More
Multi-Die Systems Key to Next Wave of Systems Innovations
These days, the term chiplets is referenced everywhere you look, in anything you read and in whatever you hear. Rightly so because the chiplets or die integration wave is taking off. Generally speaking, the tipping point that kicked off the move happened around the 16nm process technology when large monolithic SoCs started facing… Read More
MediaTek Develops Chip Utilizing TSMC’s 2nm Process, Achieving Milestones in Performance and Power Efficiency