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Synopsys MIPI Webinar

Synopsys MIPI Webinar
by Eric Esteve on 07-26-2011 at 6:05 am

Synopsys MIPI Webinar: MIPI is really getting traction

Synopsys last two acquisitions of IP vendors, former ChipIdea in 2009 (Mixed-signal product line of MIPS) and Virage Logic in 2010, have allowed to built a stronger, diversified IP port-folio. Amazingly, Synopsys has found MIPI IP product line in the basket in both cases.… Read More

Intel’s Barbed Wire Fence Strategy

Intel’s Barbed Wire Fence Strategy
by Ed McKernan on 07-21-2011 at 11:38 am

Analysts tend to make judgments regarding Intel based on an existing conventional wisdom (CW) and projecting straight line into the future. As a former Intel, Cyrix, and Transmeta processor marketing guy I would like to offer a different perspective as I have been both inside the tent looking out and outside looking in.

The current… Read More

Silicon IP to take over CAE in EDAC results… soon but not yet!

Silicon IP to take over CAE in EDAC results… soon but not yet!
by Eric Esteve on 07-20-2011 at 11:44 am

Very interesting results launched by EDAC for Q1 2011, if Computer Aided Engineering (CAE) is still the largest category with $530.6M, the second category is Silicon IP (SIP) with $371.4M, followed by IC Physical Design & Verification at $318.5M. Even more significant is the four quarter moving average results, showing … Read More

Intel Briefing: Tri-Gate Technology and Atom SoC

Intel Briefing: Tri-Gate Technology and Atom SoC
by Daniel Nenni on 07-17-2011 at 3:00 pm

Sorry to disappoint but my 2 hours at the Intel RNB was a very positive experience. It is much more fun writing negative things about industry leaders because I enjoy the resulting hate mail and personal attacks, but the candor and transparency of the Intel guys won me over. They even asked ME questions which was a bit telling. I also… Read More

And it’s Intel at 22nm but wait, Samsung slips ahead by 2nm…

And it’s Intel at 22nm but wait, Samsung slips ahead by 2nm…
by Paul McLellan on 07-12-2011 at 12:46 pm

Another announcement of interest, given all the discussion of Intel’s 22nm process around here, is that Samsung (along with ARM, Cadence and Synopsys) announced that they have taped out a 20nm ARM test-chip (using a Synopsys/Cadence flow).

An interesting wrinkle is that at 32nm and 28nm they used a gate-first process but… Read More

On-chip supercomputers, AMBA 4, Coore’s law

On-chip supercomputers, AMBA 4, Coore’s law
by Paul McLellan on 07-11-2011 at 12:45 pm

At DAC I talked with Mike Dimelow of ARM about the latest upcoming revision to the AMBA bus standards, AMBA 4. The standard gets an upgrade about every 5 years. The original ARM in 1992 ran at 10MIPS with a 20MHz clock. The first AMBA bus was a standard way to link the processor to memories (through the ARM system bus ASB) and to peripherals… Read More

Intel Twisting ARM?

Intel Twisting ARM?
by Daniel Nenni on 07-10-2011 at 11:00 am

Intel’s new Tri-Gate technology is causing quite a stir on the stock chat groups. Some have even said if Intel uses its Tri-Gate technology on only Intel processors ARM will be in deep deep trouble. These guys are “Intel Longs” of course and they are battling “Intel Shorts” with cut and paste news clips.

“ARM is in trouble & this
Read More

ARM and Mentor Team Up on Test

ARM and Mentor Team Up on Test
by Daniel Payne on 06-27-2011 at 2:31 pm

Before DAC I met with Stephen Pateras, Ph.D. at Mentor Graphics, he is the Product Marketing Director in the Silicon Test Solutions group. Stephen has been at Mentor for two years and was part of the LogicVision acquisition. He was in early at LogicVision and went through their IPO, before that he was at IBM in the mainframe… Read More

Physical IP Group at ARM

Physical IP Group at ARM
by Daniel Payne on 06-13-2011 at 5:45 pm

After lunch on Monday I met with John Heinlin, Ph.D. – VP Marketing of Physical IP Division

Back in the day I knew the founders of Artisan (VLSI Libraries) when we worked together at Silicon Compilers (Mark Templeton, John Malecki, Scott Becker).

Q: Do you favor any EDA tools for creating your IP?
A: No, we don’t really endorse a specific… Read More

GLOBALFOUNDRIES 28nm Design Ecosystem!

GLOBALFOUNDRIES 28nm Design Ecosystem!
by Daniel Nenni on 06-01-2011 at 11:00 am

GLOBALFOUNDRIES will show off its 28nm design ecosystem at #48DAC next week in San Diego. The company will feature a full design ecosystem for its 28nm High-k Metal Gate (HKMG) technology, including silicon-validated flows, process design kits (PDKs), design-for-manufacturing (DFM), and intellectual property (IP) in partnership… Read More