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Wanted by January 30th: Paper for DAC IP Track 2018!

Wanted by January 30th: Paper for DAC IP Track 2018!
by Eric Esteve on 01-25-2018 at 12:00 pm

DAC 2018 will take place in San Francisco in June (24 to 28) and you have a fantastic opportunity to present a paper in the IP track! In fact, the deadline has been extended to January 30[SUP]th[/SUP] to submit your proposal.

Let’s make it clear: you are not expected to send the completed paper by this date, just the following:

  • The title
Read More

Webinar: Fast-track SoC Verification – Reduce time-to-first-test with Synopsys VC AutoTestbench

Webinar: Fast-track SoC Verification – Reduce time-to-first-test with Synopsys VC AutoTestbench
by Bernard Murphy on 01-25-2018 at 7:00 am

There seems to be a general sense that we have the foundations for block/IP verification more or less under control, thanks to UVM standardizing infrastructure for directed and constrained-random testing, along with class libraries providing building blocks to simplify verification reuse, build sequence tests, verify register… Read More


Context is Everything – especially for autonomous vehicle IP

Context is Everything – especially for autonomous vehicle IP
by Tom Simon on 01-24-2018 at 7:00 am

GM has just announced that it will introduce a car with no steering wheel or pedals in 2019. According to their statement, they have already planned four phases of their autonomous driving system, and they will plan many more. However, before we jump into this latest car and not grab the wheel for a spin, it is reasonable to ask about… Read More


Simulation and Formal – Finding the Right Balance

Simulation and Formal – Finding the Right Balance
by Bernard Murphy on 01-23-2018 at 7:00 am

Simulation dominates hardware functional verification today and likely will continue to dominate for the foreseeable future. Meanwhile formal verification, once thought to be a possible challenger for the title, has instead converged on a more effective role as a complement to simulation. Formal excels at finding problems… Read More


Moving from FPGA’s to Embedded FPGA Fabric – How it’s Done

Moving from FPGA’s to Embedded FPGA Fabric – How it’s Done
by Tom Simon on 01-15-2018 at 12:00 pm

Buying IP is just a little bit more complicated than buying a pair of shoes. A lot of IP is configurable and requires attention to various design and configuration parameters. We live in an age where commercial soft IP is used pretty often in designs, so people have developed increasing comfort in the process that is required to achieve… Read More


Achieving ISO 26262 Certification with ASIL Ready IP

Achieving ISO 26262 Certification with ASIL Ready IP
by Eric Esteve on 01-12-2018 at 7:00 am

According with McKinsey, “analysts predict revenue growth for advanced driver assistance systems (ADAS) to be up to 29 percent, giving the segment one of the highest growth rates in the automotive and related industries.” Design cycle in automotive segment is much longer than in segments like mobile, PC or consumer. If you expect… Read More


The lofty rise of the lowly FPGA

The lofty rise of the lowly FPGA
by Tom Simon on 01-10-2018 at 7:00 am

FPGA programmable logic has served in many capacities since it was introduced back in the early 80’s. Recently, with designers looking for innovative ways to boost system performance, FPGA’s have moved front and center. This initiative has taken on new urgency with the slowing down of process node based performance gains. The… Read More


CEVA ClearVox Simplifies Voice Pickup

CEVA ClearVox Simplifies Voice Pickup
by Bernard Murphy on 01-08-2018 at 7:00 am

Voice-based control is arguably becoming another killer app, or killer app-enabler in the very significant shifts we are seeing in automation. After a bumpy start in car feature control (for navigation, phone calls, etc) and early smartphone “intelligent” assistants, voice-based interfaces now seem to be maturing into a genuinely… Read More


Getting Started with RISC-V

Getting Started with RISC-V
by Daniel Nenni on 01-06-2018 at 4:00 pm

As I mentioned before, SiFive and RISC-V are trending topics on SemiWiki.com which makes complete sense since we have been covering semiconductor IP and ARM since we first went online in January of 2011.

In total we have published 707 IP related blogs that earned 3,565,140 views (5043 views per blog average). Out of that, 254 are … Read More


CEVA Ups the Ante for Edge-Based AI

CEVA Ups the Ante for Edge-Based AI
by Bernard Murphy on 01-05-2018 at 6:00 am

AI is quickly becoming the new killer app and everyone is piling on board as fast as they can. But there are multiple challenges for any would-be AI entrepreneur:

  • Forget about conventional software development; neural nets require a completely different infrastructure and skill-sets
  • More and more of the interesting opportunity
Read More