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WP_Term Object
(
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 424
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 424
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
    [is_post] => 
)

November 5, 2019November 20, 2019

Cadence Dives Deeper at Linley Fall Processor Conference

Cadence Dives Deeper at Linley Fall Processor Conference
by Randy Smith on 11-05-2019 at 10:00 am
Categories: Cadence, Events, IP

I wrote about Cadence AI IP not long ago when I covered the Cadence Automotive Summit at the end of July (Tensilica DNA 100 Brings the AI Inference Solution for Level 2 ADAS ECUs and Level 4 Autonomous Driving, Tensilica HiFi DSPs for What I Want to Hear, and What I Don’t Want to Hear). One of those two blogs remains one of my most widely … Read More

August 27, 2019November 20, 2019

Tensilica DNA 100 Brings the AI Inference Solution for Level 2 ADAS ECUs and Level 4 Autonomous Driving

Tensilica DNA 100 Brings the AI Inference Solution for Level 2 ADAS ECUs and Level 4 Autonomous Driving
by Randy Smith on 08-27-2019 at 10:00 am
Categories: Cadence, Events, IP

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I recently wrote about Tensilica’s HiFi DSPs which played a significant role at Cadence’s Automotive Design Summit which was held on the Cadence San Jose campus at the end of July. That article focused on infotainment while briefly touching on Advanced Driver-Assistance Systems (ADAS). ADAS is NOT synonymous with… Read More

August 16, 2019November 20, 2019

Tensilica HiFi DSPs for What I Want to Hear, and What I Don’t Want to Hear

Tensilica HiFi DSPs for What I Want to Hear, and What I Don’t Want to Hear
by Randy Smith on 08-16-2019 at 10:00 am
Categories: Cadence, IP

Image Removed

It seems every day we see a new article (or ten) on autonomous driving. It is an especially hot topic, and it will happen someday. For now, we can dream about it, and many people are working on it. But for the present, the technology in a car that commands my attention is audio. I’ve been a musician since 4^th grade. I still … Read More

July 10, 2019July 9, 2019

Smart Hearing is Heating Up

Smart Hearing is Heating Up
by Bernard Murphy on 07-10-2019 at 6:00 am
Categories: AI, Cadence, IP
3 Comments

A lot of the attention in intelligent systems is on object detection in still or video images but there’s another very active area, in smart audio. Amazon and Google smart speakers may be the best-known applications but there are more obvious (and perhaps less novelty-driven) applications in enhancing the hearing devices we already… Read More

April 22, 2019June 14, 2019

Customizing and Standardizing IP with eSilicon at the Linley Conference

Customizing and Standardizing IP with eSilicon at the Linley Conference
by Camille Kokozaki on 04-22-2019 at 12:00 pm
Categories: Cadence, Events, IP

During the SoC Design Session at the just concluded Linley Spring Processor Conference in Santa Clara, Carlos Macian, Senior Director AI Strategy and Products at eSilicon, held a talk entitled ‘Opposites Attract: Customizing and Standardizing IP Platforms for ASIC Differentiation’.

Standardization is key to IP in modern … Read More

March 4, 2019

Radar is Cheaper but Autonomous Car Needs Lidar!

Radar is Cheaper but Autonomous Car Needs Lidar!
by Eric Esteve on 03-04-2019 at 7:00 am
Categories: Automotive, Cadence, IP

To replace a human driver, autonomous car will have to “see” and do it in a better way than human being. The available solution, based on camera, radar, lidar, is not perfect and need to be improved. Radar is great for “seeing” in bad weather but has insufficient resolution to distinguish distant objects. Lidar produces high-resolution… Read More

September 24, 2018

Highly Modular, AI Specialized, DNA 100 IP Core Target IoT to ADAS

Highly Modular, AI Specialized, DNA 100 IP Core Target IoT to ADAS
by Eric Esteve on 09-24-2018 at 7:00 am
Categories: AI, Automotive, Cadence, IoT, IP, Mobile

The Cadence Tensilica DNA100 DSP IP core is not a one-size-fits-all device. But it’s highly modular in order to support AI processing at the edge, delivering from 0.5 TMAC for on-device IoT up to 10s or 100 TMACs to support autonomous vehicle (ADAS). If you remember the first talks about IoT and Cloud, a couple of years ago, the IoT … Read More

July 26, 2018

Low Cost & Power NB-IoT Solution? Fusion F1 DSP based Modem!

Low Cost & Power NB-IoT Solution? Fusion F1 DSP based Modem!
by Eric Esteve on 07-26-2018 at 12:00 pm
Categories: Cadence, IoT, IP

Supporting NB-IoT requires low cost (optimized silicon footprint) and ultra-low power solution to cope with IoT device requirement. Cadence Fusion F1 DSP IP has been integrated in modem IC by two new customers, Xinyi and Rafael, gaining traction in NB-IoT market. These design-win builds on previous momentum: software GPS solution… Read More

July 5, 2018

Liberate Trio Embraces ML and Cloud

Liberate Trio Embraces ML and Cloud
by Alex Tan on 07-05-2018 at 12:00 pm
Categories: Cadence, EDA, Events, IP

Image RemovedA chain is as strong as its weakest link. This phrase resonates well in Static Timing Analysis (STA) domain, though it is about accuracy rather than durability. As timing signoff step provides the final performance readings of a design, an STA outcome is as good as its underlying components. Aside from the parasitic… Read More

May 25, 2018

Welcome DDR5 and Thanks to Cadence IP and Test Chip

Welcome DDR5 and Thanks to Cadence IP and Test Chip
by Eric Esteve on 05-25-2018 at 7:00 am
Categories: Cadence, FinFET, IP, TSMC
3 Comments

Will we see DDR5 memory (device) and memory controller (IP) in the near future? According with Cadence who has released the first test chip in the industry integrating DDR5 memory controller IP, fabricated in TSMC’s 7nm process and achieving a 4400 megatransfers per second (MT/sec) data rate, the answer is clearly YES !

Image Removed… Read More

Instance

Array
(
    [node_name] => Cadence
    [node_id] => Array
        (
            [0] => 2
            [1] => 283
        )

)

Nodes

Threads

Array ( [0] => tribe-events-list-widget-5 [1] => search-2 [2] => media_image-2 [3] => text-6 ) WP_Term Object ( [term_id] => 15 [name] => Cadence [slug] => cadence [term_group] => 0 [term_taxonomy_id] => 15 [taxonomy] => category [description] => [parent] => 157 [count] => 424 [filter] => raw [cat_ID] => 15 [category_count] => 424 [category_description] => [cat_name] => Cadence [category_nicename] => cadence [category_parent] => 157 [is_post] => )

Tribe__Events__List_Widget Instance: 5Array ( [title] => Upcoming Events [limit] => 5 [no_upcoming_events] => [featured_events_only] => [jsonld_enable] => 1 [rw_opt] => Array ( [widget_select] => 1 [cpt_page] => 1 [others_author_archive] => 1 [others_404_page] => 1 [others_blog_page] => 1 ) [display_widget_mobile] => 1 )

Array ( [title] => Upcoming Events [limit] => 5 [no_upcoming_events] => [featured_events_only] => [jsonld_enable] => 1 [rw_opt] => Array ( [widget_select] => 1 [cpt_page] => 1 [others_author_archive] => 1 [others_404_page] => 1 [others_blog_page] => 1 ) [display_widget_mobile] => 1 )

WP_Widget_Search Instance: 2Array ( [display_widget_title] => on [title] => Search Semiwiki [rw_opt] => Array ( [widget_select] => 1 [others_blog_page] => 1 [others_author_archive] => 1 [others_404_page] => 1 [cpt_page] => 1 ) [display_widget_mobile] => 1 [rw_opt_exclude] => Array ( [pageid_274495] => 1 ) )

Array ( [display_widget_title] => on [title] => Search Semiwiki [rw_opt] => Array ( [widget_select] => 1 [others_blog_page] => 1 [others_author_archive] => 1 [others_404_page] => 1 [cpt_page] => 1 ) [display_widget_mobile] => 1 [rw_opt_exclude] => Array ( [pageid_274495] => 1 ) )

WP_Widget_Media_Image Instance: 2Array ( [display_widget_title] => on [attachment_id] => 280135 [url] => https://semiwiki.com/wp-content/uploads/2019/12/SemiWiKi-Ad-07.jpg [title] => Home/Default Page Advertisement 1 [size] => full [width] => 400 [height] => 400 [caption] => [alt] => [link_type] => custom [link_url] => https://secure.thresholdsystems.com/Training/AdvancedCMOSTechnology.aspx [image_classes] => [link_classes] => [link_rel] => [link_target_blank] => 1 [image_title] => Home/Default Page Advertisement 1 [rw_opt] => Array ( [widget_select] => 1 [pageid_196276] => 1 [category_96] => 1 [category_13] => 1 [category_95] => 1 [category_12] => 1 [category_7] => 1 [category_50] => 1 [category_90] => 1 [category_89] => 1 [category_94] => 1 [category_97] => 1 [category_22] => 1 [category_6435] => 1 [category_3611] => 1 [others_blog_page] => 1 ) [display_widget_mobile] => )

WP_Widget_Text Instance: 6Array ( [title] => [text] =>

Prototyping with Intel's New 80M Gate FPGA and S2C! Analyzing PowerMOS Devices to Reduce Power Loss and Improve Reliability REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation REPLAY: Avoiding CDM (Charged Device Model) ESD Failures REPLAY: eFPGA – "What a great idea! But I have no idea how I’d use it!" REPLAY: Ensuring System-level Security Through Hardware/Software Security Verification REPLAY: Fabless: The Transformation of the Semiconductor Industry REPLAY: The Brave New World of Customized Memory REPLAY: Embedded FPGA: The Fabric for Optimized Machine Learning REPLAY: VLSI Design Methodology Development REPLAY: Lightspeed Data Sync - Design Workspace Problems Solved! REPLAY: Desinging Complex SoCs and Dealing with Multiple File Formats? REPLAY: How ASIC/SoC Prototyping Solutions Can Help You! REPLAY: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso® REPLAY: Taiwan ESD Workshop Recording REPLAY: Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction REPLAY: Text: A Year of Breakfast Bytes by Paul McLellan (Free PDF Version) REPLAY: Finding Your Way Through Verification REPLAY: Concerned about IP security threats for your SoCs? REPLAY: Achronix: Accelerate Data Processing Algorithms using FPGAs with 2D Network-on-Chip REPLAY: PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior REPLAY: Thermal-induced Reliability Challenges and Solutions for Advanced IC Design REPLAY: Choose the Right ASIC Manufacturing Model for Your Business [filter] => 1 [visual] => 1 [rw_opt] => Array ( [widget_select] => 1 [others_front_page] => 1 [cpt_page] => 1 [others_blog_page] => 1 ) [display_widget_mobile] => 1 )

Array ( [title] => [text] =>

Array ( [0] => rpwe_widget-9 [1] => gtranslate-3 [2] => media_image-8 [3] => xfrp_widget-2 [4] => better_recent_comments-2 ) WP_Term Object ( [term_id] => 15 [name] => Cadence [slug] => cadence [term_group] => 0 [term_taxonomy_id] => 15 [taxonomy] => category [description] => [parent] => 157 [count] => 424 [filter] => raw [cat_ID] => 15 [category_count] => 424 [category_description] => [cat_name] => Cadence [category_nicename] => cadence [category_parent] => 157 [is_post] => )

Recent_Posts_Widget_Extended Instance: 9Array ( [title] => Trending Now [title_url] => [ignore_sticky] => 1 [exclude_current] => 1 [limit] => 5 [offset] => 10 [order] => DESC [orderby] => date [post_type] => Array ( [0] => post ) [post_status] => publish [cat] => Array ( ) [tag] => Array ( ) [taxonomy] => [excerpt] => [length] => 10 [date] => [date_relative] => [date_modified] => [readmore] => [readmore_text] => Read More [comment_count] => [thumb] => [thumb_height] => 55 [thumb_width] => 55 [thumb_default] => http://images/semiwiki-small.png [thumb_align] => rpwe-alignleft [styles_default] => 1 [cssID] => [css_class] => [css] => .rpwe-block ul{ list-style: none !important; margin-left: 0 !important; padding-left: 0 !important; } .rpwe-block li{ border-bottom: 1px solid #eee; margin-bottom: 10px; padding-bottom: 10px; list-style-type: none; } .rpwe-block a{ display: inline !important; text-decoration: none; } .rpwe-block h3{ background: none !important; clear: none; margin-bottom: 0 !important; margin-top: 0 !important; font-weight: 400; font-size: 12px !important; line-height: 1.5em; } .rpwe-thumb{ border: 1px solid #eee !important; box-shadow: none !important; margin: 2px 10px 2px 0; padding: 3px !important; } .rpwe-summary{ font-size: 12px; } .rpwe-time{ color: #bbb; font-size: 11px; } .rpwe-comment{ color: #bbb; font-size: 11px; padding-left: 5px; } .rpwe-alignleft{ display: inline; float: left; } .rpwe-alignright{ display: inline; float: right; } .rpwe-aligncenter{ display: block; margin-left: auto; margin-right: auto; } .rpwe-clearfix:before, .rpwe-clearfix:after{ content: ""; display: table !important; } .rpwe-clearfix:after{ clear: both; } .rpwe-clearfix{ zoom: 1; } [before] => [after] => [rw_opt] => Array ( [widget_select] => 1 [others_front_page] => 1 [others_author_archive] => 1 [others_404_page] => 1 [pageid_275979] => 1 ) [display_widget_mobile] => )

GTranslateWidget Instance: 3Array ( [title] => Google Translate [rw_opt] => Array ( [pageid_275979] => 1 [others_front_page] => 1 [others_author_archive] => 1 [others_404_page] => 1 [widget_select] => 1 ) [display_widget_mobile] => )

WP_Widget_Media_Image Instance: 8Array ( [display_widget_title] => on [attachment_id] => 280148 [url] => https://semiwiki.com/wp-content/uploads/2019/12/Intel-80M-Webinar-300x300.jpg [title] => [size] => medium [width] => 400 [height] => 400 [caption] => [alt] => [link_type] => custom [link_url] => https://register.gotowebinar.com/register/1882953647871074061?source=SemiWIki+S2C [image_classes] => [link_classes] => [link_rel] => [link_target_blank] => [image_title] => Home/Default Page Advertisement 4 [display_widget_mobile] => [rw_opt] => Array ( [widget_select] => 1 [others_front_page] => 1 [pageid_275979] => 1 ) )

XF2_Latest_Posts_Widget Instance: 2Array ( [title] => Recent Forum Threads [title_url] => [ignore_sticky] => 0 [exclude_current] => 0 [limit] => 10 [offset] => 0 [order] => [orderby] => ID [post_type] => Array ( [0] => post ) [post_status] => [cat] => Array ( ) [tag] => Array ( ) [taxonomy] => [excerpt] => [length] => 0 [date] => [date_relative] => [date_modified] => [readmore] => [readmore_text] => [comment_count] => [thumb] => [thumb_height] => 0 [thumb_width] => 0 [thumb_default] => [thumb_align] => [styles_default] => [cssID] => [css_class] => [css] => [before] => [after] => [display_widget_mobile] => 1 [rw_opt] => Array ( [widget_select] => 1 [others_front_page] => 1 [pageid_274495] => 1 [pageid_275979] => 1 ) [sluglist] => ["jobs-dashboard"] [rw_opt_exclude] => Array ( [pageid_274493] => 1 ) )

Array ( [title] => Recent Forum Threads [title_url] => [ignore_sticky] => 0 [exclude_current] => 0 [limit] => 10 [offset] => 0 [order] => [orderby] => ID [post_type] => Array ( [0] => post ) [post_status] => [cat] => Array ( ) [tag] => Array ( ) [taxonomy] => [excerpt] => [length] => 0 [date] => [date_relative] => [date_modified] => [readmore] => [readmore_text] => [comment_count] => [thumb] => [thumb_height] => 0 [thumb_width] => 0 [thumb_default] => [thumb_align] => [styles_default] => [cssID] => [css_class] => [css] => [before] => [after] => [display_widget_mobile] => 1 [rw_opt] => Array ( [widget_select] => 1 [others_front_page] => 1 [pageid_274495] => 1 [pageid_275979] => 1 ) [sluglist] => ["jobs-dashboard"] [rw_opt_exclude] => Array ( [pageid_274493] => 1 ) )

Widget_Better_Recent_Comments Instance: 2Array ( [title] => Recent Article Comments [number] => 10 [avatar] => [date] => 1 [comment] => 1 [link] => 1 [display_widget_mobile] => 1 [rw_opt] => Array ( [widget_select] => 1 [others_front_page] => 1 [pageid_275979] => 1 ) [rw_opt_exclude] => Array ( [pageid_274493] => 1 ) )

Array ( [title] => Recent Article Comments [number] => 10 [avatar] => [date] => 1 [comment] => 1 [link] => 1 [display_widget_mobile] => 1 [rw_opt] => Array ( [widget_select] => 1 [others_front_page] => 1 [pageid_275979] => 1 ) [rw_opt_exclude] => Array ( [pageid_274493] => 1 ) )

Cadence Dives Deeper at Linley Fall Processor Conference

Tensilica DNA 100 Brings the AI Inference Solution for Level 2 ADAS ECUs and Level 4 Autonomous Driving

Tensilica HiFi DSPs for What I Want to Hear, and What I Don’t Want to Hear

Smart Hearing is Heating Up

Customizing and Standardizing IP with eSilicon at the Linley Conference

Radar is Cheaper but Autonomous Car Needs Lidar!

Highly Modular, AI Specialized, DNA 100 IP Core Target IoT to ADAS

Low Cost & Power NB-IoT Solution? Fusion F1 DSP based Modem!

Welcome DDR5 and Thanks to Cadence IP and Test Chip

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