Semiwiki 400x100 1 final
WP_Term Object
(
    [term_id] => 106
    [name] => FPGA
    [slug] => fpga
    [term_group] => 0
    [term_taxonomy_id] => 106
    [taxonomy] => category
    [description] => 
    [parent] => 0
    [count] => 339
    [filter] => raw
    [cat_ID] => 106
    [category_count] => 339
    [category_description] => 
    [cat_name] => FPGA
    [category_nicename] => fpga
    [category_parent] => 0
    [is_post] => 
)
FPGA
Posted on

I could show you the FPGA, but then I’d have to configure you

I could show you the FPGA, but then I’d have to configure you
by Don Dingee on 10-31-2013 at 6:00 pm
Categories: Aldec, EDA, FPGA

One of the present ironies of the Internet of Things is as it seeks to connect every device on the planet, we are still designing those things with largely unconnected EDA tools. We may share libraries and source files on a server somewhere, but that is just the beginning of connection.

It is not surprising that synthesis tools from… Read More

Posted on

Pigs Fly. Altera Goes with ARM on Intel 14nm

Pigs Fly. Altera Goes with ARM on Intel 14nm
by Paul McLellan on 10-29-2013 at 7:00 am
Categories: Arm, FPGA, Intel, IP

Altera announced in February that they would be using Intel as a foundry at 14nm. Historically they have used TSMC. Then in June they announced the Stratix 10 family of FPGAs that they would build on the Intel process. At the Globalpress summit in May I asked Vince Hu about their processor strategy. Here is what I wrote about itat the… Read More

Posted on

Always-on Context-aware Sensors in Your Phone

Always-on Context-aware Sensors in Your Phone
by Paul McLellan on 10-16-2013 at 8:00 am
Categories: FPGA

Smartphones are smart but they are about to get smarter. The next big thing in mobile phones is to have a rich sensor environment: proximity, temperature and humidity, atmospheric pressure, light color, cover, gyroscope, magnetometer, accelerometer, ambient light, gesture and more. Some of these are already here, of course,… Read More

Posted on

Xilinx’s Vivado HLS Will Float Your FPGA

Xilinx’s Vivado HLS Will Float Your FPGA
by Luke Miller on 09-23-2013 at 8:30 pm
Categories: FPGA, Xilinx

Very rarely does the FPGA designer, especially with respect to RADAR, think of the FPGA as a floating point processor. Just to be sure I asked my 6 year old and she agreed. But you know what, the Xilinx FPGAs float. Go try it, order some up and fill up the tub.

Anyways I purpose a duel to the avid VHDL coder. I want you to design me a Sine(x) … Read More

Posted on

Xilinx At 28nm: Keeping Power Down

Xilinx At 28nm: Keeping Power Down
by Paul McLellan on 09-08-2013 at 2:26 pm
Categories: Ansys, Inc., FPGA, TSMC, Xilinx

Almost without exception these days, semiconductor products face strict power and thermal budgets. Of course there are many issues with dynamic power but one big area that has been getting increasingly problematic is static power. For various technical reasons we can no longer reduce the voltage as much as we would like from one… Read More

Posted on

FPGAs The Life Savers

FPGAs The Life Savers
by Luke Miller on 08-27-2013 at 1:00 pm
Categories: FPGA, Xilinx

Silicon dominates our lives, CPU’s, GPU’s are in the limelight but the unsung hero is the FPGA. They simply do the work where other silicon dare not tread, as they are unfit for the task. Never send a boy to do a man’s job.

For a moment, if we can, just for a few minutes perhaps we can break away from the social media bubble… Read More

Posted on

More to the story than bigger FPGA-based prototyping

More to the story than bigger FPGA-based prototyping
by Don Dingee on 08-19-2013 at 5:00 pm
Categories: EDA, FPGA, Synopsys

Still not convinced on the value of FPGA-based prototyping systems, or using older technology? I’ve been trying to find the story beyond just bigger, badder FPGAs in a box that you pour RTL into – and found some hints in a webinar on the Synopsys HAPS-70 from earlier this year.… Read More

Posted on

Accelerating SoC Simulation Times

Accelerating SoC Simulation Times
by Daniel Payne on 08-15-2013 at 2:43 pm
Categories: Aldec, EDA, FPGA

There never seems to be enough time in a SoC project to simulate all of the cycles and tests that you want to run, so any technique to accelerate each run is welcomed. You can just wait for your software-based RTL simulator to finish running, or you can consider using a hardware-based accelerator approach. I learned more about one such… Read More

Posted on

Coke vs. Pepsi; Xilinx vs. Altera

Coke vs. Pepsi; Xilinx vs. Altera
by Luke Miller on 08-02-2013 at 10:00 am
Categories: FPGA, Xilinx

I have many thoughts on this topic, so forgive the word salad that may ensue. I have been thinking about Coca-Cola lately, partly because I bought an old coke machine (I’m one of those guys… pray for my wife). I am amazed that Coke which was founded in 1886, still has a secret recipe. I like that, but boy every time the web reveals the coke… Read More

Posted on

Xilinx picks another winner…

Xilinx picks another winner…
by Luke Miller on 07-31-2013 at 7:00 pm
Categories: FPGA, Xilinx

Just as important as block RAMs, IO and DSP48’s is what interconnect or fabric is going to be used when considering SoC FPGA designs. I think Xilinx has found the winning combination. What is paramount to the new SoC FPGA methodologies is not only the challenge of moving huge amounts of data around; we are now to consider data… Read More