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WP_Term Object
(
    [term_id] => 106
    [name] => FPGA
    [slug] => fpga
    [term_group] => 0
    [term_taxonomy_id] => 106
    [taxonomy] => category
    [description] => 
    [parent] => 0
    [count] => 341
    [filter] => raw
    [cat_ID] => 106
    [category_count] => 341
    [category_description] => 
    [cat_name] => FPGA
    [category_nicename] => fpga
    [category_parent] => 0
    [is_post] => 
)
FPGA
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Is FPGA Intel Next Big Thing for IoT ?

Is FPGA Intel Next Big Thing for IoT ?
by Eric Esteve on 11-04-2016 at 4:00 pm
Categories: FPGA, IoT

I write this article in reaction to another article from Seeking Alpha titled “Intel Next Big Thing”. I have extracted this from the article:

The IoT space is growing rapidly with the advent of connected cars, smart homes and a variety of connected devices and appliances. However, before a full-blown ecosystem around these devices… Read More

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FPGAs for a few thousand devices more

FPGAs for a few thousand devices more
by Don Dingee on 10-24-2016 at 4:00 pm
Categories: Aldec, Automotive, EDA, FPGA, IoT, Xilinx

An incredibly pervasive trend at last year’s ARM TechCon was the IoT, and I expect this year to bring even more of the same, but with a twist. Where last year was mostly focused on ultra-low power edge devices and the mbed ecosystem, this year is likely to show a better balance of ideas across all three IoT tiers. I also expect a slew of … Read More

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Adding DSP hardware shrinks energy for MCU core

Adding DSP hardware shrinks energy for MCU core
by Don Dingee on 10-14-2016 at 4:00 pm
Categories: eFPGA, Flex Logix, FPGA, IoT, IP

ARM’s Cortex-M4 processor core represented quite a breakthrough in digital signal controller technology when launched in 2010. Adding a single-cycle multiplier and SIMD instructions enabled basic DSP algorithms while retaining the low power benefits of an MCU. New technology circa 2016 – embedded programmable logic – can… Read More

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CEO Interview: Geoff Tate of Flex Logix

CEO Interview: Geoff Tate of Flex Logix
by Daniel Nenni on 10-10-2016 at 7:00 am
Categories: CEO Interviews, eFPGA, Flex Logix, FPGA, IP

Geoff Tate Flexlogix

This is the second in series of interviews we will do with executives inside the fabless semiconductor ecosystem. Geoff Tate was the founding CEO of Rambus and is now CEO and co-founder of Flex Logix (embedded FPGA). This one should be of great interest due to the recent $16.7B acquisition of Altera by Intel. We all now know the importance… Read More

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Microsoft, FPGAs and the Evolution of the Datacenter

Microsoft, FPGAs and the Evolution of the Datacenter
by Bernard Murphy on 10-03-2016 at 12:00 pm
Categories: FPGA

When we think of datacenters, we think of serried ranks of high-performance servers. Recent announcements from Google (on the Tensor Processing Unit), Facebook and others have opened our eyes to the role that specialized hardware and/or GPUs can play in support of deep/machine learning and big data analytics. But most of us would… Read More

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Intel Altera FPGA at the heart of an autonomous Audi A8

Intel Altera FPGA at the heart of an autonomous Audi A8
by Claudio Avi Chami on 10-02-2016 at 4:00 pm
Categories: Automotive, Foundries, FPGA, Intel

Audi announced its piloted driving technology at CES 2015. The Audi Prologue includes the Advanced Driver Assistance System Platform (zFAS), co-developed with TTTech. The zFAS board is based on four devices: an Nvidia k1 processor and Infineon Aurix processor, Mobileye’s EyeQ3 for vision processing, and an Altera Cyclone … Read More

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CCIX shows up in ARM CMN-600 interconnect

CCIX shows up in ARM CMN-600 interconnect
by Don Dingee on 09-30-2016 at 4:00 pm
Categories: Arm, FPGA, IP

All the hubbub about FPGA-accelerated servers prompts a big question about cache coherency. Performance gains from external acceleration hardware can be wiped out if the system CPU cluster is frequently taking hits from cache misses after data is worked on by an accelerator.

ARM’s latest third-generation CoreLink CMN-600 … Read More

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Up front phases improve CDC analysis

Up front phases improve CDC analysis
by Don Dingee on 09-19-2016 at 4:00 pm
Categories: Aldec, EDA, FPGA

Many tools find clock domain crossings (CDCs) in FPGA designs. Some don’t find the right ones since they don’t comprehend things like in-house synchronizer constructs. Some find too many based on misunderstanding intent, inaccurate constraints, and other factors that lead to noise.… Read More

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VHDL parameterized PWM controller

VHDL parameterized PWM controller
by Claudio Avi Chami on 09-18-2016 at 7:00 am
Categories: FPGA

Digital outputs can either go ON or OFF. Analog signals, on the other side, can smoothly assume multiple values in a range. There is a technique that emulates analog behavior with a digital output. That technique is PWM, namely, Pulse Width Modulation. It can be implemented as pulses with varying ‘high’ and ‘low’… Read More