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FPGA
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A Self-Contained Software-Driven Prototype

A Self-Contained Software-Driven Prototype
by Bernard Murphy on 04-26-2017 at 7:00 am
Categories: Aldec, Automotive, EDA, Prototyping, Xilinx

You’re building an IP, subsystem or SoC and you want to use a prototype together with a software testbench to drive extensive validation testing. I’m not talking here about the software running on the IP/SoC processor(s); the testbench should wrap around the whole DUT. This is a very common requirement. The standard approach to… Read More

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Seven Reasons to Use FPGA Prototyping for ASIC Designs

Seven Reasons to Use FPGA Prototyping for ASIC Designs
by Daniel Payne on 03-28-2017 at 12:00 pm
Categories: EDA, FPGA, Open-Silicon

Using an FPGA to prototype your next hardware design is a familiar concept, extending all the way back to the time that the first FPGAs were being produced by Xilinx and Altera. There are multiple competitors in the marketplace for FPGA prototyping, so I wanted to discern more about what the German-based company PRO DESIGN had to … Read More

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Aldec Swings for the Fences

Aldec Swings for the Fences
by Bernard Murphy on 03-17-2017 at 7:00 am
Categories: Aldec, Automotive, EDA, FPGA, IoT

In today’s fast-moving technology markets, companies who are prepared to step up to opportunity can break out of traditional bounds to become players in bigger and fast-growing markets. It looks to me like Aldec is putting itself on that path. They have announced an end-to-end hardware/software co-verification solution… Read More

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Six Reasons to Consider Using FPGA Prototyping for ASIC Designs

Six Reasons to Consider Using FPGA Prototyping for ASIC Designs
by Daniel Payne on 03-15-2017 at 12:00 pm
Categories: EDA, Events, FPGA, Open-Silicon

There’s no doubt that programmable logic in FPGAs have transformed our electronics industry for the better. If you do ASIC designs then there’s always the pressure of getting first silicon correct, with no functional or timing bugs, because bugs will cause expensive re-spins and delay time to market. ASIC designers… Read More

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Power and Performance Optimization for Embedded FPGA’s

Power and Performance Optimization for Embedded FPGA’s
by Tom Dillinger on 02-22-2017 at 12:00 pm
Categories: eFPGA, Flex Logix, FPGA, IP

Last month, I made a “no-brainer” forecast that 2017 would be the year in which embedded FPGA (eFPGA) IP would emerge as a key differentiator for new SoC designs (link to the earlier article here).

The fusion of several technical and market factors are motivating design teams to incorporate programmable logic functionality… Read More

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Aldec Rounds Out ALINT-PRO Checker

Aldec Rounds Out ALINT-PRO Checker
by Bernard Murphy on 02-16-2017 at 7:00 am
Categories: Aldec, EDA, FPGA

If there’s anyone out there who still doesn’t accept the importance of static RTL verification in the arsenal of functional verification methods, I haven’t met any recently. That wasn’t the case in my early days in this field. Back then I grew used to hearing “I don’t make mistakes in my RTL”, “I’ll catch that in simulation”, “My editor… Read More

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Xilinx vs Altera Update 2017

Xilinx vs Altera Update 2017
by Daniel Nenni on 02-15-2017 at 7:00 am
Categories: FPGA, Intel, Xilinx

I truly miss the Xilinx versus Altera war of words (competition at its finest) and competition is what makes the fabless semiconductor ecosystem truly great, absolutely. So with great disappointment I read the Intel Analyst Day transcript published by Bloomberg last week. It is attached at the bottom in case you are interested… Read More

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FPGA Design Gets Real

FPGA Design Gets Real
by Tom Simon on 02-08-2017 at 12:00 pm
Categories: EDA, FPGA, Synopsys

FPGA’s have become an important part of system design. It’s a far cry from how FPGA’s started out – as glue logic between discrete logic devices in the early days of electronic design. Modern day FPGA’s are practically SOC’s in their own right. Frequently they come with embedded processor cores, sophisticated IO cells, DSP,… Read More

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Four Steps for Logic Synthesis in FPGA Designs

Four Steps for Logic Synthesis in FPGA Designs
by Daniel Payne on 01-30-2017 at 12:00 pm
Categories: EDA, FPGA, Synopsys

I remember meeting Ken McElvain at Silicon Compilers for the first time back in the 1980’s, he was a gifted EDA tool developer that did a lot of coding including logic synthesis, a cycle-based simulator and ATPG. Mentor Graphics acquired Silicon Compilers with Ken included, and he continued to create another logic synthesis… Read More