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SEMICON West seemed a little slow last week but maybe it was just me. I’m sure SEMI will come out with record breaking numbers but I did not see it in the exhibit hall (see the video). What I did see was hundreds of exhibitors but I had no idea what they did. San Francisco again was very congested and smelly. I talked to a friend who is in public… Read More
At DAC 2018, Synopsys held a lunch panel discussing verification challenges faced by the industry leaders, their adopted approaches and the overall verification technology trends. This panel of industry experts from Intel, AMD, Samsung, STM and Qualcomm also shared their viewpoints on what drives the SoC complexity and how… Read More
The 2018 VLSI Technology conference was held in Hawaii in June and is one of the premier conferences covering integrated circuit process technology and circuit design. The Complementary FET (CFET) is an emerging option to continue logic scaling into the next decade. At the conference imec, GLOBALFOUNDRIES, Tokyo Electron and… Read More
The stock market hates uncertainty most of all. In the absence of the known, the market will assume the worst or close to it. Right now there is a lot of uncertainty that continues to have more downside beta than upside beta. Everybody we spoke to at Semicon wakes up in the morning wondering what tweet was sent at 5AM that will impact their… Read More
We attended Semicon West Monday and Tuesday, the annual show for the semi equipment industry. Its very clear from discussions with all our sources in the industry that confirm that Samsung has put the brakes on spending on memory and that message was reinforced by declines in their expected profitability due to weaker memory pricing.… Read More
I attended on Monday, June 25, DAC’s Opening Day, a Cadence-sponsored Lunch panel. Ann Steffora Mutschler (Semiconductor Engineering) was the Moderator and the Panelists were Jim Hogan (Vista Ventures), David Lacey (HP Enterprise), Shigeo Oshima (Toshiba Memory Corp), Paul Cunningham (Cadence).… Read More
Welcome to my newly relocated column, I am so excited about my new relationship with Daniel Nenni, and the other esteemed bloggers on SemiWiki. For those who do not know me, I have been a featured columnist on another EDA portal for the past 12-plus years, and in EDA for 20-plus years. As the leading recruiter in our industry, (or so … Read More
My IC design career started out with circuit design of DRAMS, so I got to quickly learn all about transistor-level design at the number one IDM in the world, Intel at the time. In the early days, circa 1978 we circuit designers actually had few EDA tools, mostly a SPICE circuit simulator followed by manual extraction, manual netlisting,… Read More
Getting your tape-out done on time is hard, but can it be made easier? That was the main topic of Mentor’s Calibre Panel held at DAC 2018, attended by a few key players in IC design ecosystem: Bob Stear, VP of Marketing at Samsung represented the foundry side; from the IP side, Prasad Subramaniam, VP of eSilicon for R&D and Technology;… Read More
This year I signed books in the Fractal booth (compliments of Fractal) and let me tell you it was quite an experience. IP quality is a very touchy subject and the source of many more tape-out delays than I had imagined. As it turns out, commercial IP is the biggest offender which makes no sense to me whatsoever. Even more shocking, one… Read More
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Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet