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It’s no coincidence that the TSMC Symposium is right after the Q1 earnings call. This will allow TSMC to talk more freely and they certainly will, my opinion. It is a very interesting time in the semiconductor industry and TSMC, being the bellwether, can tell us what will happen the rest of the year and give us some 2020 insights.… Read More
Dr. Cheng Wang, Co-Founder and SVP Engineering at Flex Logix, presented the second talk in the ‘AI at the Edge’ session, at the just concluded Linley Spring Processor Conference, highlighting the InferX X1 Inference Co-Processor’s high throughout, low cost, and low power. He opened by pointing out that existing inference solutions… Read More
On the Sunday evening at IEDM last year, TechInsights held a reception in which Arabinda Das and Jeongdong Choe gave presentations that attracted a roomful of conference attendees.
This is the second part of the review of Jeongdong’s talk, we covered NAND flash technology in the last post. Jeongdong is a Senior Technical… Read More
On the Sunday evening at IEDM last year, TechInsights held a reception in which Arabinda Das and Jeongdong Choe gave presentations that attracted a roomful of conference attendees. Arabinda was first up, giving a talk on the “10-year Journey of Apple’s iPhone and Innovations in Semiconductor Technology”, followed by Jeongdong… Read More
The basic principles used for neural networks have been understood for decades, what have changed to make them so successful in recent years are increased processing power, storage and training data. Layered on top of this is continued improvement in algorithms, often enabled by dramatic hardware performance improvements.… Read More
Many of us have engineering degrees and are well paid to maintain a deep but narrow focus into a specific domain, but what about the big picture, like industry trends and emerging challenges? Well, DAC56 has just the thing to deliver us a front row seat to the big picture, and it’s contained in both the Keynotes and SKYtalks.… Read More
The big three EDA vendors are constantly putting more of their tools in the cloud in order to speed up the design and verification process for chip designers, but how do engineering teams approach using the cloud for functional verification tests and regressions? At the recent Cadence user group meeting (CDNLive) there was a presentation… Read More
Like many others, we have often wondered why the PMOS fins on advanced microprocessors from Intel are narrower than the NMOS fins (6nm versus 8nm). This unusual dimensional difference first occurred at the 14nm node and it coincided with the introduction of Solid State Doping (SSD) of the fins at this node.
We have concluded that… Read More
An informal “Fireside Chat” like no other featuring Jim Hogan, managing partner of Vista Ventures, LLC., and Paul Cunningham, Cadence’s corporate vice president and general manager of the system verification group, is in the works for Wednesday, April 10.
Hosted by the ESD Alliance, a SEMI Strategic Association Partner, at … Read More
I plan to attend to the GSA European Forum in Munich (April 15-16), so I first looked at the event description and at the impressive speakers list. In such event, the goal is at 50% to listen, and 50% to network with the speakers and the other attendant. The center of gravity is clearly semiconductor, but the event involved speakers … Read More
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Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot