Banner Electrical Verification The invisible bottleneck in IC design updated 1
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Alphawave IP is Enabling 224Gbps Serial Links with DSP

Alphawave IP is Enabling 224Gbps Serial Links with DSP
by Mike Gianfagna on 12-14-2020 at 10:00 am

Alphawave IP is Enabling 224Gbps Serial Links with DSP

Alphawave IP is a new member of the SemiWiki community. You can learn about the company and their CEO, Tony Pialis in this interview by Dan Nenni. Design & Reuse did a virtual IP-SOC Conference recently and Tony presented. The D&R event had a very strong lineup of presenters. They supplemented the prepared video presentations… Read More


Design Considerations for 3DICs

Design Considerations for 3DICs
by Tom Dillinger on 12-14-2020 at 6:00 am

LVS flow phases

The introduction of heterogeneous 3DIC packaging technology offers the opportunity for significant increases in circuit density and performance, with corresponding reductions in package footprint.  Yet, the implementation of a complex 3DIC product requires a considerable investment in methodology development for all… Read More


IEDM 2020 Starts this Weekend

IEDM 2020 Starts this Weekend
by Scotten Jones on 12-10-2020 at 6:00 am

IEDM 2020 Logo

As I have discussed before, I believe that IEDM is the premier technical conference for understanding leading edge process technologies. Beginning this coming weekend, this year’s edition of IEDM will be held virtually, and I highly recommend attending.

The conference held a press briefing last Monday. The tutorial and short… Read More


The Practitioners View of DAC – Design, IP and Embedded

The Practitioners View of DAC – Design, IP and Embedded
by Mike Gianfagna on 12-07-2020 at 10:00 am

The First DAC

Next year will mark the 58th year for the Design Automation Conference. It’s hard to wrap your head around the fact this event dates back to 1964, when rock ‘n roll was new, cars were big and computers were even bigger. In its early days, the event was called the Design Automation Workshop. Pictured above is the cover of the very first… Read More


Analog Bits is Supplying Analog Foundation IP on the Industry’s Most Advanced FinFET Processes

Analog Bits is Supplying Analog Foundation IP on the Industry’s Most Advanced FinFET Processes
by Mike Gianfagna on 12-02-2020 at 10:00 am

Analog Bits is Supplying Analog Foundation IP on the Industrys Most Advanced FinFET Processes

The industry recently concluded a series of technology events for the all the major foundries.  Done as virtual events this year, each one provided a significant update on technology platforms, roadmaps and ecosystem partnerships. These events are quite valuable to chip design teams who need to be aware of the latest in process,… Read More


Webinar: Menta is Breaking New Ground with eFPGA IP Using Adaptive DSP

Webinar: Menta is Breaking New Ground with eFPGA IP Using Adaptive DSP
by Mike Gianfagna on 11-23-2020 at 10:00 am

Webinar Menta is Breaking New Ground with eFPGA IP Using Adaptive DSP

Menta is a unique embedded FPGA (eFPGA) company. Their eFPGA IP is based completely on standard cells provided by the foundry, the customer or a third party – no custom cells or custom cell characterization is needed. They also don’t require any specific library, process step or metal stack. All this makes Menta’s eFPGA IP easy to… Read More


Silicon Catalyst Hosts Semiconductor Industry Forum – A View to the Future … it’s about what’s next®

Silicon Catalyst Hosts Semiconductor Industry Forum – A View to the Future … it’s about what’s next®
by Mike Gianfagna on 11-20-2020 at 10:00 am

A View to the Future ... its about whats next

Silicon Catalyst has been hosting semiconductor forums since 2018. At these events, a group of industry leaders gathers to discuss trends in the semiconductor industry and what the future may hold as a result. I recently had an opportunity to speak with Pete Rodriguez, CEO at Silicon Catalyst. Pete explained that these forums … Read More


Achieving 112Gbps PAM4 Channels with Achronix FPGAs and Samtec Interconnect

Achieving 112Gbps PAM4 Channels with Achronix FPGAs and Samtec Interconnect
by Mike Gianfagna on 11-19-2020 at 10:00 am

Achieving 112Gbps PAM4 Channels with Achronix FPGAs and Samtec Interconnect

They say that getting there is half the fun. On December 1, Achronix and Samtec will present a webinar on this topic in the context of high-performance front panel to midplane and midplane to backplane channel design. Technology, materials and system design will all be discussed with a focus on achieving 112Gbps PAM4 channels with… Read More


Powering the Next Generation of Hearables and Wearables with Chipus

Powering the Next Generation of Hearables and Wearables with Chipus
by Mike Gianfagna on 11-16-2020 at 10:00 am

Powering the Next Generation of Hearables and Wearables with Chipus

Chipus is an interesting company. It’s been around since 2008 and focuses on mixed-signal ASICs, intellectual property blocks and IC design services. They are headquartered on the island of Florianopolis, which is described as the most dense startup ecosystem in Brazil. The company has substantial skills in analog and mixed… Read More


Mentor Offers Next Generation DFT with Streaming Scan Network

Mentor Offers Next Generation DFT with Streaming Scan Network
by Tom Simon on 11-12-2020 at 10:00 am

Streaming Scan Network

Design for test (DFT) requires a lot of up-front planning that can be difficult to alter if testing needs or performance differ from initial expectations. Hierarchical methodologies help in many ways including making it easier to reduce on chip resources such as the number of test signals. Also, hierarchical test allows for speed-ups… Read More