Ever increasing data handling demands make creating hardware for many applications extremely difficult. In an upcoming webinar Achronix, a leading supplier of FPGA’s, talks about the data handling requirements for AI/ML applications – which are growing at perhaps one of the highest rates of all. Just looking at all data… Read More
Live 58th Design Automation Conference Coverage!
My beautiful first mate and I will be together at DAC this year. Her first DAC was 1985 in Las Vegas and we lived happily ever after. SemiWiki bloggers Tom Dillinger and Daniel Payne will also be at DAC attending sessions and meeting with exhibiting companies to learn and blog about the latest innovations inside the semiconductor … Read More
Low Power High Performance PCIe SerDes IP for Samsung Silicon
No matter how impressive the specifications are for an SoC, the power performance and area of the finished design all depend on the IP selected for the IO blocks. In particular, most SOCs designed for consumer and enterprise applications rely heavily on PCI Express. Because PCIe analog IP is critical to design success, Samsung … Read More
Ansys to Present Multiphysics Cloud Enablement with Microsoft Azure at DAC
Ansys and Microsoft collaborated extensively over the past year to optimize and test Ansys’ signoff multiphysics simulation tools on the Azure cloud. Microsoft has invited Ansys to present the joint results in Azure’s DAC booth theater in San Francisco this year.
Two presentations are planned: covering the enablement of Ansys… Read More
Webinar: The Backstory of PCIe 6.0 for HPC, From IP to Interconnect
PCIe, or peripheral component interconnect express, is a very popular high-speed serial computer expansion bus standard. The width and speed the standard supports essentially defines the throughput for high-performance computing (HPC) applications. The newest version, PCIe 6.0 promises to double the bandwidth that the… Read More
Siemens EDA will be returning to DAC this year as a Platinum Sponsor.
The 38th Design Automation Conference is next week and this one is for the record books. Having been virtual the last two years, next week we will meet live once again. I think we may have all taken for granted the value of live events but now we know how important they are on both a professional and human level, absolutely.
“The… Read More
Silicon Catalyst Hosts an All-Star Panel December 8th to Discuss What Happens Next?
Each year, Silicon Catalyst assembles a panel of industry luminaries to discuss important questions about the future. The charter of the Silicon Catalyst Industry Forum is to: “create a platform for broad-topic dialog among all stakeholders involved in the semiconductor industry value chain. The Forum topics focus on technical… Read More
WEBINAR: Using Design Porting as a Method to Access Foundry Capacity
There have always been good reasons to port designs to new foundries or processes. These reasons have included reusing IP in new projects, moving an entire design to a smaller node to improve PPA, or second sourcing manufacturing. While there can be many potential business motivations for any of the above, in today’s environment… Read More
Numerical Sizing and Tuning Shortens Analog Design Cycles
By any measure analog circuit design is a difficult and complex process. This point is driven home in a recent webinar by MunEDA. Michael Pronath, VP Products and Solutions at MunEDA, lays out why, even with the assistance of simulators, analog circuit sizing and tuning can consume weeks of time in what can potentially be a non-convergent… Read More
Taiwan Semiconductor Outlook May 1988
This is an interesting piece of TSMC history. From 1987 to 1988 James E. Dykes served as the first President and Chief Executive Officer of Taiwan Semiconductor Manufacturing Company Ltd.
Taiwan Semiconductor Outlook
by James E. Dykes
President & Chief Executive Officer
Taiwan Semiconductor Manufacturing Company
Given… Read More
Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet