I had the opportunity to speak with Pete Rodriguez and Alain Labat in regards to the upcoming webinar on M&A. I have worked with both Pete and Alain in the past so I can tell you personally that this event will be well worth your time. This is truly an all star cast with a collective experience base with billions of dollars worth of … Read More
EDA Flows for 3D Die Integration
Background
The emergence of 2.5D heterogeneous die integration using a silicon (or organic) interposer has enabled unique system architectures. The term “More than Moore” has been used to describe the circuit density and cost advantages of leveraging multiple die in the package, the die potentially in different process technologies. … Read More
How can Semiconductor Manufacturers add new Capacity to Meet Demand as Quickly as Possible?
The causes of the chip shortage crisis have been widely discussed, but what about specific solutions? How can semiconductor manufacturers add new capacity to meet demand as quickly as possible?
While there is a lot of talk about investment in building new chip plants, these traditional methods of manufacturing capacity growth… Read More
VLSI Technology Symposium – Imec Alternate 3D NAND Word Line Materials
At the 2021 VLSI Technology Symposium, Imec presented on Ruthenium (Ru) and Molybdenum (Mo) as alternate Word Line (WL) materials for 3D NAND Flash “First Demonstration of Ruthenium and Molybdenum Word lines Integrated into 40nm Pitch 3D NAND Memory Devices”. I had an opportunity to interview one of the authors: Maarten Rosmeulen.… Read More
TSMC Design Considerations for Gate-All-Around (GAA) Technology
The annual VLSI Symposium provides unique insights into R&D innovations in both circuits and technology. Indeed, the papers presented are divided into two main tracks – Circuits and Technology. In addition, the symposium offers workshops, forums, and short courses, providing a breadth of additional information.
At… Read More
VLSI Technology Symposium – Imec Forksheet
FinFETs devices are reaching their limits for scaling. Horizontal Nanosheets (HNS) are a type of Gate All Around (GAA) device that offers better scaling and performance per unit area. HNS is the logical next step from FinFETs because HNS processing is similar to FinFETs with a limited number of process changes required.
At the … Read More
On Standards and Open-Sourcing. Verification Talks
At Veriest we host VERIFICATION MEETUPS periodically to share verification wisdom. In our virtual meetings we’ve had hundreds of attendants from the US, Europe, Israel, India, and China. Most recently we were able to host a live event in Israel – I want to share feedback from that meeting.
We started with two presentations:… Read More
VLSI Symposium – TSMC and Imec on Advanced Process and Devices Technology Toward 2nm
At the 2021 Symposium on VLSI Technology and Circuits in June a short course was held on “Advanced Process and Devices Technology Toward 2nm-CMOS and Emerging Memory”. In this article I will review the first two presentations covering leading edge logic devices. The two presentations are complementary and provide and excellent… Read More
Resist Development for High-NA EUV
The successful transition to a new fabrication process from development to high volume manufacturing requires a collective, collaborative effort among process engineers, equipment manufacturers, and especially, chemical suppliers. Of particular importance is the chemistry of the photoresist materials and their interaction… Read More
Webinar: Learn about NVMe conformance Testing
Several years ago I recall upgrading my aging MacBook Pro laptop from using a Hard Disk Drive (HDD) to a Solid State Drive (SSD) that used Non-Volatile Memory (NVM). Oh what a speed improvement when pushing that On button each morning to start the work day, or clicking an App to see it launch without delay. Another epiphany for me in … Read More
Facing the Quantum Nature of EUV Lithography