At Hot Chips 2025, Philippe Sauter of ETH Zürich presented Basilisk, a project that may redefine what’s possible with open-source hardware. Basilisk is a 34 mm² RISC-V SoC fabricated at IHP Microelectronics on its open-source 130nm BiCMOS process in Germany. Basilisk, named after the Greco-Roman mythical creature known… Read More
How AI Workloads Shape Hardware Architecture
The evolution of AI workloads has profoundly influenced hardware design, shifting from single-GPU systems to massive rack-based clusters optimized for parallelism and efficiency. As outlined in this Hot Chips 2025 tutorial, this transformation began with foundational models like AlexNet in 2012 and continues with today’s… Read More
GlobalFoundries 2025 Update GTS25
“GTS25 brings together leaders from across the semiconductor industry to share their insights on the latest technology trends that enable GF to design the essential chips the world relies on to live, work and connect.”
GlobalFoundries (GF), a leading contract semiconductor manufacturer, plays an important… Read More
Perforce and Siemens at #62DAC
Wednesday was the last day at #62DAC for me and I attended an Exhibitor Session entitled, Engineering the Semiconductor Digital Thread, which featured Vishal Moondhra, VP Solutions Engineering of Perforce IPLM and Michael Munsey, VP Semiconductor Industry at Siemens Digital Industries. Instead of just talking from slides,… Read More
Synopsys Enables AI Advances with UALink
The evolution of hyperscale data center infrastructure to support the processing of trillions of parameters for large language models has created some rather substantial design challenges. These massive processing facilities must scale to hundreds of thousands of accelerators with highly efficient and fast connections.… Read More
Perforce Webinar: Can You Trust GenAI for Your Next Chip Design?
GenAI is certainly changing the world. Every day there are new innovations in the use of highly trained models to do things that seemed impossible just a short while ago. As GenAI models take on more tasks that used to be the work of humans, there is always a nagging concern about accuracy and bias. Was the data used to train the model … Read More
Software-defined Systems at #62DAC
Modern EVs are prime examples of software-defined systems, so I attended a #62DAC panel session hosted by Siemens to learn more from experts at Collins Aerospace, Arm, AMD and Siemens. Here’s the list of panelists that span several domains, and what follows is my paraphrase of the discussion topics.
Panel Discussion
Q: How does… Read More
Unlocking Efficiency and Performance with Simultaneous Multi-Threading
An Akeana hosted webinar on Simultaneous Multi-Threading (SMT) provided a comprehensive deep dive into the technical, commercial, and strategic significance of SMT in the evolving compute landscape. Presented by Graham Wilson and Itai Yarom, the session was not only an informative overview of SMT architecture and use cases,… Read More
DAC TechTalk – A Siemens and NVIDIA Perspective on Unlocking the Power of AI in EDA
AI was everywhere at DAC. Presentations, panel discussions, research papers and poster sessions all had a strong dose of AI. At the DAC Pavillion on Monday two heavy weights in the industry, Siemens and NVIDIA took the stage to discuss AI for design, both present and future. What made this event stand out for me was the substantial… Read More
Synopsys Webinar – Enabling Multi-Die Design with Intel
As we all know, the age of multi-die design has arrived. And along with it many new design challenges. There is a lot of material discussing the obstacles to achieve more mainstream access to this design architecture, and some good strategies to conquer those obstacles. Synopsys recently published a webinar that took this discussion… Read More


The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival