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For 20 years there has been the Electronic Design Process Symposium. It has been held each April and for the last few years at least has always been in Monterey at the Monterey Beach Resort. This year it is Thursday and Friday April 18th/19th.
The keynote on the first day is by Ivo Bolsens of Xilinx on The All-programmable SoC —… Read More
I used my secret powers (being a blogger will get you a press pass) to go to the first day of the SPIE conference on advanced lithography a couple of weeks ago. Everything that happens to with process nodes seems to be driven by lithography, and everything that happens in EDA is driven by semiconductor process. It is the place to find … Read More
Those of us who spend a lot of time at EDA marketing events cannot help but notice the dramatic shrinking of the floor space, and to some extent attendance, at the major EDA shows such as DAC and DATE. DAC used to occupy both the north and south halls of Moscone Center when in San Francisco, but now only takes up one hall. So, I did not have… Read More
One of the privilages of blogging for SemiWiki is invitations to the top conferences around the world including the International Solid-State Circuits Conference (ISSCC) in San Francisco this week. Amazing, this conference is older than I am:
ISSCC 2013 is the 60th Conference in an incredibly long-lasting series. Following… Read More
As you know, I’ve been a bit of a bear about what is happening to wafer costs at 20nm and below. At the Common Platform Technology Forum last week there were a number of people talking about this in presentations and at Harvey Jones’s “fireside chat”.
At the press lunch I asked about this. There are obviously… Read More
“Innovations for Next Generation Scaling”
The 2013 Forum today (Feb 5, 2013) started with a presentation by Dr. Gary Patton, VP, IBM Semiconductor Research & Development Center. Gary very clearly articulated the two irresolvable challenges the industry now faces:
These … Read More
I was at the Common Platform Technology Forum this week. One of the most interesting sessions is IBM’s Gary Patton giving an overview of the state of semiconductor fabrication. Then, at lunchtime, he is one of the people that the press can question. In this post, I’m going to focus on Extreme Ultra-Violet (EUV) lithography.… Read More
Can’t make it to Santa Clara? Join us online!
The detailed 2013 CPTF agenda is now up in preparation for the February 5th event at the Santa Clara Convention Center. This is one of the rare times that you can get a free lunch! Watch this quick video to see what is in store for us this year. Dr. Paul McLellan and I will be there so please… Read More
Going to DAC? I just booked my plane ticket last weekend since flights from the Bay Area to wherever DAC is are so often overbooked. It’s in Austin this year in case you’ve been living under a rock. There are lots of reasons to go, from the academic conference to the world’s biggest EDA exhibition. And here is one … Read More
I was at DesignCon in Santa Clara today and listened to Jonah Alben of NVIDIA’s keynote on what their approach is to improving design methodology. He started by pointing out that most companies underinvest in EDA (and he includes NVIDIA in this). Partially it is complaceny: that last chip taped out so we know we can do it again.… Read More
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Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot