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Synopsys IP Designs Edge AI 800x100
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Untangling snags earlier and reducing area by 10%

Untangling snags earlier and reducing area by 10%
by Don Dingee on 01-30-2014 at 6:00 pm

The over 20 years of experience behind Synopsys Design Compiler is getting a new look for 2014, and we had a few minutes with Priti Vijayvargiya, director of product marketing for RTL synthesis, to explore what’s in the latest version of the synthesis tool.

Previewed today, Synopsys Design Compiler 2013.12 continues to target … Read More


First Verdi Interoperability Apps Developer Forum

First Verdi Interoperability Apps Developer Forum
by Paul McLellan on 01-30-2014 at 11:47 am

Way back when SpringSoft was still SpringSoft and not Synopsys they launched Verdi Interoperability Apps (VIA) and an exchange for users to share them open-source style. I wrote about it back in 2011 when it was announced. Today, Synopsys announced the first developer forum for VIA. It will be held at SNUG on Wednesday, March 26,… Read More


Special Interest Group for HSPICE at DesignCon in Two Weeks

Special Interest Group for HSPICE at DesignCon in Two Weeks
by Daniel Payne on 01-13-2014 at 8:00 pm

DesignCon brings together engineers from around the world that are interested in IC design, package design and board design, plus the signal integrity issues of creating high-speed systems. In just two weeks there’s a Special Interest Group(SIG) just for users of HSPICE in their tool flow, and it meets for three hours during… Read More


A little FPGA-based prototyping takes the eXpress

A little FPGA-based prototyping takes the eXpress
by Don Dingee on 12-26-2013 at 9:00 am

Ever sat around waiting for a time slot on the one piece of big, powerful, expensive engineering equipment everyone in the building wants to use? It’s frustrating for engineers, and a project manager’s nightmare: a tool that can deliver big results, and a lot of schedule juggling.… Read More


Known Unknowns and Unknown Unknowns

Known Unknowns and Unknown Unknowns
by Paul McLellan on 12-11-2013 at 3:18 pm

Donald Rumsfeld categorized what we knew into known unknowns and unknown unknowns. In a chip design, those unknown unknowns can bite you and leave you with a non-functional design, perhaps even intermittent failures which can be among the hardest problems to debug.

Chips are too big to do any sort of full gate-level simulation,… Read More


Designing a DDR3 System to Meet Timing

Designing a DDR3 System to Meet Timing
by Daniel Payne on 12-11-2013 at 12:00 pm

My very first thought when hearing about HSPICE is using it for IC simulation at the transistor-level, however it can also be used to simulate a package or PCB interconnect very accurately, like in the PCB layout of a DDR3 system where timing is critical. I attended a webinar this morning that was jointly presented by Zuken and Synopsys… Read More


Conquering errors in the hierarchy of FPGA IP

Conquering errors in the hierarchy of FPGA IP
by Don Dingee on 12-02-2013 at 10:00 am

FPGA design today involves not only millions of gates on the target device, but thousands of source files with RTL and constraints, often generated by multiple designers or third party IP providers. With modules organized in some logical way describing the design, designers brace themselves for synthesis and a possible avalanche… Read More


Social Media at Synopsys

Social Media at Synopsys
by Daniel Payne on 11-15-2013 at 4:35 pm

When I talk about social media and mention Synopsys you may quickly think of Karen Bartleson, the Senior Director of Community Marketing, because she:

Read More

M-PCIe, Data Converters, and USB 3.0 SSIC at IP SoC 2013

M-PCIe, Data Converters, and USB 3.0 SSIC at IP SoC 2013
by Eric Esteve on 10-31-2013 at 9:38 am

Synopsys is taking IP-SOC 2013 seriously, as the company will hold several presentations, starting with a Keynote: “Virtual Prototyping – A Reality Check”, by Johannes Stahl, Director, Product Marketing, System-Level Solutions, Synopsys, highlighting current industry practice around putting virtual prototyping to work… Read More


ARC EM SEP Processor, Safety Ready Solution for Automotive

ARC EM SEP Processor, Safety Ready Solution for Automotive
by Eric Esteve on 10-30-2013 at 5:24 am

If you are familiar with Processor IP core, you certainly know DesignWare ARC EM4 core, 32-bit CPU that SoC designers can optimize for a wide range of uses, and differentiate by using patented configuration technology to tailor each ARC core instance to meet specific performance, power and area requirements. If you develop a product… Read More