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arc v 800x100 High Quality (1) 
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Synopsys
Posted on

Deploying 14nm FinFETs in your Next Mobile SoC

Deploying 14nm FinFETs in your Next Mobile SoC
by Daniel Payne on 06-19-2013 at 11:05 am
Categories: EDA, FinFET, Foundries, GlobalFoundries, Synopsys

At DAC in Austin a design company, foundry and EDA vendor teamed up to present their experiences with 14nm FinFETs during a breakfast on Tuesday.

Panelists included:

… Read More
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Formality Ultra, Streamline Your ECOs

Formality Ultra, Streamline Your ECOs
by Paul McLellan on 06-17-2013 at 8:00 am
Categories: EDA, Synopsys

One of the most challenging stages in an SoC design is achieving timing closure. Actually design closure is perhaps a better term since everything needs to come together such as clock tree, power nets, power budget and so on. Changes made to the design are known as ECOs (which stands for engineering change orders, a term that comes… Read More

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Hardware Assisted Verification

Hardware Assisted Verification
by Paul McLellan on 06-10-2013 at 9:00 pm
Categories: Cadence, EDA, Events, Siemens EDA, Synopsys

On the Tuesday of DAC I moderated a panel session on Hardware Assisted Verification in 10 Years: More Need, More Speed. Although this topic obviously could include FPGA-based prototyping, in fact we spent pretty much the whole time talking about emulation. Gary Smith, on Sunday night, actually set up things by pointing out that… Read More

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AMS IC Simulation Update from Synopsys at DAC

AMS IC Simulation Update from Synopsys at DAC
by Daniel Payne on 06-10-2013 at 6:19 pm
Categories: EDA, Synopsys

Last year at DAC we didn’t really know the circuit simulation roadmap for Synopsys because of all the EDA company acquisitions, however this year it’s clear to me that:

  • HSPICE continues on, although it’s a lower performance circuit simulator than FineSim
  • FineSim from Magma is well-loved, and faster than HSPICE
… Read More
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First FinFETs Manufactured at #50DAC!

First FinFETs Manufactured at #50DAC!
by Daniel Nenni on 06-09-2013 at 5:00 pm
Categories: EDA, Events, Sage DA, Solido, Synopsys


This was my 30[SUP]th[/SUP] DAC and the second most memorable. The most memorable was my second DAC (1985) in Las Vegas with my new bride. We had a romantic evening ending with ice cream sundaes at midnight that we still talk about. This year SemiWiki had Dr. Paul McLellan, Dr. Eric Esteve, Daniel Payne, Don Dingee, Randy Smith, and… Read More

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You can tune a piano, but you can’t tune a cache without help

You can tune a piano, but you can’t tune a cache without help
by Don Dingee on 05-30-2013 at 8:30 pm
Categories: EDA, Synopsys

Once upon a time, designing a product with a first generation SoC on board, we were trying to use two different I/O peripherals simultaneously. Seemed simple enough, but things just flat out didn’t work. After days spent on RTFM (re-reading the fine manual), we found ourselves at the absolute last resort: ask our FAE.

After about… Read More

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Enabling 14nm FinFET Design

Enabling 14nm FinFET Design
by Daniel Payne on 05-28-2013 at 12:54 pm
Categories: EDA, Samsung Foundry, Synopsys

There’s never a dull moment in the foundry race to offer FinFET processes that enable leading-edge SoC design. Today I attended a webinar hosted by Samsung and Synopsys on how to enable 14nm FinFET design. The two speakers were Dr. Kuang-Kuo Lin from Samsung and Dr. Henry Sheng from Synopsys.


Dr. Kuang-Kuo Lin, Samsung


Dr.… Read More

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Complete Schedule of Synopsys 2013 DAC Events, Panels & Paper Participation (Free Food!)

Complete Schedule of Synopsys 2013 DAC Events, Panels & Paper Participation (Free Food!)
by Daniel Nenni on 05-19-2013 at 9:01 pm
Categories: EDA, Synopsys

Funny story, @ #49DAC I saw Aart with a very relaxed look on his face looking at the exhibit hall and in my mind he was thinking, “Mine, all mine!” But I digress……. Synopsys is the #1 EDA company for a reason and here is the supporting data for that hypothesis:

Synopsys is committed to accelerating Innovation… Read More

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Challenges of 20nm IC Design

Challenges of 20nm IC Design
by Daniel Payne on 04-29-2013 at 11:38 am
Categories: EDA, Synopsys

Designing at the 20nm node is harder than at 28nm, mostly because of the lithography and process variability challenges that in turn require changes to EDA tools and mask making. The attraction of 20nm design is realizing SoCs with 20 billion transistors. Saleem Haider from Synopsys spoke with me last week to review how Synopsys… Read More

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Gigahertz FFT rates on a 500MHz budget

Gigahertz FFT rates on a 500MHz budget
by Don Dingee on 04-23-2013 at 8:30 pm
Categories: EDA, Synopsys

A basic building block of any communication system today is the fast Fourier transform, or FFT. A big advantage of FPGA implementations of FFTs is they can be scaled and tuned for the task at hand, optimizing data flow, resource use, and power consumption. Scaled, that is, up to the clock speed of the FPGA – or so it would seem.

Today’s… Read More