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Synopsys
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Synopsys Verification Continuum

Synopsys Verification Continuum
by Paul McLellan on 09-26-2014 at 4:00 pm
Categories: EDA, Synopsys

Verification spans a number of different technologies, from virtual platforms, RTL simulation, formal techniques, emulation and FPGA prototyping. Going back a few years, most of these technologies came from separate companies and one effect of this was that moving the design from one verification environment to another required… Read More

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Explaining HAPS-DX in an elevator

Explaining HAPS-DX in an elevator
by Don Dingee on 09-24-2014 at 7:00 am
Categories: EDA, Synopsys

Every development team has been through this challenge: finding a tool that looks fantastic, then heading off to the manager one or two levels up who has enough signature authority for the purchase order. Signatures for amounts reading more than a couple of trailing zeros on POs are rarely free, or painless. … Read More

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AMD Design IP Deal with Virage Logic… Oops… Synopsys

AMD Design IP Deal with Virage Logic… Oops… Synopsys
by Eric Esteve on 09-23-2014 at 9:59 am
Categories: EDA, Synopsys

Whoever has said that history never repeats itself should read this recent PR from AMD! The news can be summarized in three points:

  • Multi-year agreement gives AMD access to a range of Synopsys design IP including interface, memory compiler, logic library and analog IP for advanced FinFET process nodes
  • Synopsys acquires rights
… Read More
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Design & EDA Collaboration Advances Mixed-Signal Verification through VCS AMS

Design & EDA Collaboration Advances Mixed-Signal Verification through VCS AMS
by Pawan Fangaria on 09-07-2014 at 8:00 pm
Categories: Arm, EDA, Foundries, IP, STMicroelectronics, Synopsys

Last week it was a rare opportunity for me to attend a webinar where an SoC design house, a leading IP provider and a leading EDA tool provider joined together to present on how the tool capabilities are being used for advanced mixed-signal simulation of large designs, faster with accuracy. It’s always been a struggle to combine design… Read More

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Synopsys VC VIP for Memory

Synopsys VC VIP for Memory
by Paul McLellan on 09-04-2014 at 7:01 am
Categories: EDA, Synopsys

Synopsys have been gradually broadening their portfolio of verification IP (VIP). It is 100% native SystemVerilog with native debug using Verdi (that was acquired from SpringSoft last year, now fully integrated into Verification Compiler). It has native performance with VCS. Going forward there are source code test suites.… Read More

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FinFETs for your Next SoC

FinFETs for your Next SoC
by Daniel Payne on 08-24-2014 at 7:00 am
Categories: EDA, FinFET, Synopsys

Planar CMOS processes have been offered for decades now, and all the way down through the 28nm node it has been riding the benefits of Moore’s Law. A few years back we started hearing from Intel about TriGate (aka FinFET) starting at the 22nm node as a way to use a more 3D processing approach for transistors instead of planar CMOS.… Read More

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Synopsys Earnings

Synopsys Earnings
by Paul McLellan on 08-21-2014 at 12:00 pm
Categories: EDA, Synopsys

The perfect quarterly results are to slightly beat the consensus for earnings and profit, and not say anything negative about guidance for the upcoming quarter. Synopsys delivered all that with their latest quarter yesterday. Revenue was $521M versus $483M last year, giving solid growth of over 8%. Non-GAAP earnings per share… Read More

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Transaction-based Emulation

Transaction-based Emulation
by Paul McLellan on 08-14-2014 at 7:01 am
Categories: EDA, Synopsys

Verification has been going through a lot of changes in the last couple of years. Three technologies that used to be largely contained in their own silos have come together: simulation, emulation and virtual-platforms.

Until recently, the workhorse verification tool was simulation. Emulation had its place but limits on capacity… Read More

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End-to-end look at Synopsys ProtoCompiler

End-to-end look at Synopsys ProtoCompiler
by Don Dingee on 07-28-2014 at 9:00 pm
Categories: EDA, Synopsys

Usually, we get the incremental story in news: this new release is x percent better at this or that than the previous release, and so on. Often missing is the big picture, telling how the pieces all tie together. Synopsys took on that challenge in their latest FPGA-based prototyping webinar. … Read More

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Hybrid Emulation

Hybrid Emulation
by Paul McLellan on 07-25-2014 at 9:01 am
Categories: EDA, Synopsys

Hybrid emulation is when part of the system is run in the emulator and part of the system is run in a virtual prototype. Typically a model of the processor(s) is run in the virtual platform and then the rest of the design is modeled by running the RTL on the emulator. I talked to Tom Borgstrom at Synopsys about what technology they have … Read More