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Synopsys
Posted on

Synopsys Earnings Call Q1 2015

Synopsys Earnings Call Q1 2015
by Paul McLellan on 02-20-2015 at 7:00 am
Categories: EDA, Synopsys

Synopsys announced their results yesterday. Their 2014 already ended, this is the end of their fiscal first quarter. On the call were Aart, one of Synopsys’s two co-CEOs, the other being Chi-Foon Chan; and Trac Pham, the new CFO on his first earnings call.

Synopsys’s results were good. A quick look at the results. Revenue was $542M… Read More

Posted on

Do You Need a Silicon Catalyst?

Do You Need a Silicon Catalyst?
by Daniel Nenni on 02-14-2015 at 7:00 pm
Categories: EDA, Foundries, IP, Synopsys, TSMC

Lately there has been significant concern over the rising costs of designing in silicon and the troubling decline in venture investments in semiconductors. These alarming trends include fewer IPOs, a falloff in the amount and frequency of early stage seed investments, and comparatively low industry organic growth rates. A … Read More

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Dealing with FPGA IP in all its forms

Dealing with FPGA IP in all its forms
by Don Dingee on 02-12-2015 at 10:00 pm
Categories: EDA, FPGA, Synopsys

One of the recurring themes I see here in the pages of SemiWiki and elsewhere is this pitched, bordering on religious battle between Altera and Xilinx. Just because both are FPGA technologies, the tendency is to put them in the same bucket, drawing direct comparisons between them. Some folks say there is no comparison; Xilinx has… Read More

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How Well is HSPICE Tracking Current Design Trends?

How Well is HSPICE Tracking Current Design Trends?
by Tom Simon on 02-11-2015 at 10:00 pm
Categories: EDA, Synopsys

For about 5 years now Synopsys has held an HSPICE SIG event in conjunction with DesignCon. It features a small vendor faire with companies that partner with Synopsys on HSPICE flows. They also have a dinner with industry/customer speakers and provide an update on HSPICE development. Lastly there is a Q&A where customers get… Read More

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What’s New with Static Timing Analysis

What’s New with Static Timing Analysis
by Daniel Payne on 01-30-2015 at 7:00 am
Categories: EDA, Synopsys

When I hear the phrase Static Timing Analysis (STA) the first EDA tool that comes to mind is PrimeTimefrom Synopsys, and this type of tool is essential to reaching timing closure for digital designs by identifying paths that are limiting chip performance. Sunil Walia, PrimeTime ADV marketing lead spoke with me by phone on Thursday… Read More

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How Imagination tested the PowerVR Series6XT

How Imagination tested the PowerVR Series6XT
by Don Dingee on 01-23-2015 at 10:00 pm
Categories: EDA, Synopsys

We have been hearing for some time about the Synopsys HAPS-70 and how they have co-created the hardware and software architecture for FPGA-based prototyping with their customers. Now, we see details published by Synopsys on how they collaborated with Imagination on the design of the PowerVR Series6XT GPU.

The first thing to come… Read More

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Prototyping Kits to Accelerate IP Development & Integration into SoCs

Prototyping Kits to Accelerate IP Development & Integration into SoCs
by Pawan Fangaria on 01-04-2015 at 10:00 am
Categories: EDA, IP, Synopsys

With growing SoC size, complexity, software and hardware content in it and shrinking time-to-market, the SoC design completion in time has become increasingly dependent on IP which need to be sourced (internally or externally), customized according to the design need and integrated together into the SoC. While IP providers… Read More

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Synthesizing rad-tolerant RTL for FPGAs

Synthesizing rad-tolerant RTL for FPGAs
by Don Dingee on 12-09-2014 at 4:00 pm
Categories: EDA, FPGA, Synopsys

The maiden voyage of NASA’s Orion spacecraft brought a raft of articles about how the flight computer inside is “no smarter than your phone,” running on wheezing IBM PowerPC 750FX processors. NASA’s deputy manager for Orion avionics, Matt Lemke, admits the configuration is already obsolete – at least in commercial terms. … Read More

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Synopsys Q4 Earnings

Synopsys Q4 Earnings
by Paul McLellan on 12-06-2014 at 11:02 am
Categories: EDA, Synopsys

Synopsys announced their earnings a couple of days ago. This is actually also the end of their fiscal year. They had quarterly earnings of $539M meaning that they did just over $2B for the year. Their guidance for fiscal 2015 is revenue between $2.185B to $2.225B. They said that about 80% of that revenue is already in backlog.

But it… Read More

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Design Rule Checking (DRC) Meets New Challenges

Design Rule Checking (DRC) Meets New Challenges
by Daniel Payne on 12-02-2014 at 7:00 am
Categories: EDA, Synopsys

The traditional batch-oriented DRC process run as a final check to ensure compliance with foundry yield goals is quickly moving toward a concurrent DRC process performed early and often throughout design, especially at the 28 nm and smaller process nodes. What are the technology factors causing this change?

  • Increasing number
… Read More