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“We intend to grow revenue 14% to 15%, continue to drive notable ops margin expansion and aim for approximately 16% non-GAAP earnings per share growth.”
Synopsys, Inc. (NASDAQ:SNPS) Q4 2022 Earnings Call Transcript
Synopsys is the EDA bellwether since they report early and are the #1 EDA and #1 IP company. In addition to crossing… Read More
Configurable processors are hot now, in no small part thanks to RISC-V. Which is an ISA rather than a processor, but let’s not quibble. Arm followed with configurability in Cortex-X. Both were considerably preceded (a couple of decades) by Synopsys ARC® RISC CPUs and CEVA DSPs. Each stressed configurability as a differentiator… Read More
New EDA product launches are always an exciting time, and I could hear the energy and optimism from the voice of Manoj Chacko at Synopsys in our Zoom call about Synopsys PrimeClosure. During the physical implementation phase for IC designs there’s a big challenge to reach timing closure, and with advanced nodes the number… Read More
Over the last few years, the design of application-specific ICs as well as high-performance CPUs and other complex ICs has hit a proverbial wall. This wall is built from several issues: first, chip sizes have grown so large that they can fill the entire mask reticle and that could limit future growth. Second, the large chip size impacts… Read More
SiMa.ai just announced that they achieved first silicon success on their new MLSoC, for AI applications at the edge, using Synopsys’ design, verification, IP and design services solutions. Notably this design includes the Synopsys ARC® EV74 processor (among other IP) for vision processing. SiMa.ai claim their platform, now… Read More
Verification has long been the most time-consuming and often resource-intensive part of chip development. Building out the infrastructure to tackle verification can be a costly endeavor, however. Emerging and even well-established semiconductor companies must weigh the Cost-of-Results (COR) against Time-to-Results
Synopsys Fusion Compiler offers advanced optimizations to achieve the best PPA (power, performance, area) on today’s high-performance cores and interconnect designs. However, advanced transformation techniques available in synthesis such as retiming, multi-bit registers, advanced datapath optimizations, etc. are
I consider Dr. Aart de Geus one of the founding fathers of EDA and one of the most interesting people in the semiconductor industry. So it is not a surprise that Aart was chosen to attend the CHIPs Act signing at the White House.
Here is his current corporate bio:
Since co-founding Synopsys in 1986, Dr. Aart de Geus has expanded Synopsys… Read More
The design and characterization of RF circuits is a complex process that requires an RF designer to overcome a variety of challenges. Not only do they face the complexities posed by advanced semiconductor processes and the need to meet the demanding requirements of modern wireless standards, designers must also account for electromagnetic… Read More
Whether we realize it or not, everyday applications we use depend on data gathered by sensors. We can bet that pretty much every application uses at least a couple of different types of sensors, if not more. That is because different types of sensors are better suited to collect data depending on the application, the environment … Read More
Podcast EP219: How Synopsys Addresses Debug and Coverage Closure Challenges with Robert Ruiz
Podcast EP188: The New Demands for Memory Design and the Synopsys Approach with Anand Thiruvengadam
Podcast EP185: DRAM Scaling, From Atoms to Circuits with Synopsys’ Dr. Victor Moroz
Podcast EP178: An Overview of Advanced Power Optimization at Synopsys with William Ruby
Podcast EP169: How Are the Standards for the Terabit Era Defined?
Podcast EP152: An Informal Conversation with Aart de Geus on AI and Multi-Die at SNUG
Podcast EP148: The Synopsys View of High-Performance Communication and the Role of Chiplets
Podcast EP141: The Role of Synopsys High-Speed SerDes for Future Ethernet Applications
Podcast EP240: Challenges and Strategies to Address New Embedded Memory Architectures with Mark Han
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