If you are a TSMC customer, no doubt you have heard TSMC is requiring lithography and planarity analysis for all 45nm designs. Their website says customers can either run it themselves, or contract TSMC services to do it. The most cost-effective way would be for the customers to run it themselves, but some might not have the resources… Read More
Electronic Design Automation
Effects of Inception
I finally got to watch the critically acclaimed sci-fi movie “Inception” last weekend and life has not been the same since. Without giving away too much detail for the benefit of those who have not watched it yet, the main plot involves dreams within dreams within dreams – three levels to be precise—to “incept” an idea into … Read More
TSMC OIP Conference 2010 Critique!
Okay, this is more of a, “What I would do if I was TSMC” than a critique, but I needed a one word descriptor for the title. This was the third TSMC OIP Conference and I would guess about 250 people attended. This was the first time I have seen TSMC in “reactive” mode versus “proactive” leadership mode, so I was a bit disappointed. TSMC is … Read More
Critical Area Analysis and Memory Redundancy
Simon Favre, one of our Calibre Technical Marketing Engineers, presented a paper on Critical Area Analysis and Memory Redundancy at the 2010 IEEE North Atlantic Test Workshop in Hopewell Junction, NY, just up the road from Fishkill. As Simon says…
Fishkill, New York. IBM is in Fishkill. IBM invented Critical Area Analysis in what,… Read More
Semiconductor Realization!
Insanity is doing the same thing over and over again and expecting different results (Albert Einstein). Given that statement, according to John Bruggeman (Cadence CMO and EDA360 Chief Anarchist) the semiconductor industry is INSANE!
This year the EDA Tech Forum and the Global Semiconductor Alliance Expo were not only on the … Read More
GlobalFoundries Exposed, Part II!
EDA CEO panels are usually rather dull but this one definitely held my interest. It was standing room only and I was surrounded by familiar faces from not only EDA and IP company executives, but also representatives from the top semiconductor companies around the world! The theme of course was collaboration, promoting the GFI “IDM-Like”… Read More
Atrenta Semiconductor Design in 3D!
My vote for most compelling technology at #47DAC is 3D technology. No, I don’t mean Hollywood-style 3D, I’m talking about vertical stacked-die system on chip design. This design approach basically means putting different parts of the system on different silicon substrates, so you can use the right technology for each part, and… Read More
Personal Message to Carl Icahn RE: MENT
According to an amended 13S filing, you now own 7.9% of Mentor Graphics, up from 6.86% disclosed on May 27th. Just what are you thinking!?!?!? Clearly you are a smart guy and you pretty much invented the game of corporate raidership, but EDA? Mentor Graphics? EDA does not need you, Mentor Graphics does not need you, I do not need you … Read More
Synopsys Acquires Virage Logic!
Overshadowing the acquisition of Denali by Cadence, Synopsys, the #2 semiconductor IP provider acquires Virage Logic, the #3 IP provider. Virage brings the #1 embedded SRAM, #1 BIST, #1 Logic Libraries, #1 DDR, #1 NVM, the ARC CPU cores and audio/video interface technology, and all the AMS IP from the NXP acquisition.
Under the… Read More
TSMC Unveils First Ever AMS Reference Flow!
As a quick follow-up to my blog TSMC Extends Open Innovation Platform, TSMC today announced the Analog/Mixed Signal Reference Flow 1.0., another key collaborative component of TSMC’s Open Innovation Platform™.
The TSMC AMS Design Flow 1.0’s design package is integrated seamlessly on top of the 28nm interoperable process design… Read More
Elon Musk Given CHIPS Act & AI Oversight – Mulls Relocation of Taiwanese Fabs