If we look at SoC design evolution, we have certainly successfully passed several steps: from transistor by transistor IC design using Calma up to design methodology based on the integration of 500K + gates IP like PCIe gen-3 Controller, one out of several dozens of IP integrated in today’ SoC for Set-Top-Box or Wireless Application… Read More
Electronic Design Automation
Apache Low Power Webinars
For those of you who didn’t get to DAC you can catch up on low power issues with Apache’s series of low-power webinars taking place late in July. All webinars are at 11am Pacific Time. Full details and registration on the Apache website here.… Read More
Synopsys IP Strategy 2012
Synopsys is the dominant player in the commercial EDA and semiconductor IP markets so it is always interesting to hear what John Koeter, Vice President of Marketing for IP, Services and System Level Solutions, has to say. John presented “The Role of IP in a Changing Landscape” at the SemiCO IMPACT Conference and I talked to him again… Read More
Chip Synthesis at DAC
I visited Oasys Design Systems and talked to Craig Robbins, their VP sales. For the first time this year, Oasys has a theater presentations and demos of RealTime Designer which are open to anyone attending the show. In previous years, they have had suite demos for appropriately qualified potential customers but outside they have… Read More
TSMC Threater Presentation: Lorentz Solution!
Lorentz Solution presented at TSMC’s DAC 2012 Open Innovation Platform Theater. The presenter was Lorentz Sales Director, Tom Simon. He presented what Lorentz calls its Electromagnetic Design and Analysis Platform. One of the main points of the talk was the cooperative work that Lorentz does with TSMC.
Robustness, Reliability and Yield at DAC
On Wednesday at DAC I met with Bob Slee, distributor and Michael Siu, AE for MunEDA to get an update on what’s new. MunEDA has EDA software for:
- Schematic porting
- Nominal circuit analysis
- Nominal circuit optimization
- Statistical circuit analysis
- Statistical circuit optimization
- IP porting
- Circuit model generation
Methodics update at DAC
Fergus Slorach, CTO and Founder of Methodics met with me at DAC on Wednesday afternoon to provide an update on software configuration management for hardware designers.… Read More
Photo and Video Overview of DAC 2012
Sunday Night – you have to network at the EDAC kick-off party.… Read More
Analog FastSPICE update at DAC
Paul Estrada, COO of Berkeley DA met with me on the final day of DAC to provide an update. BDA coined the phrase Analog FastSPICE and have continued to dominate that market segment in the world of SPICE circuit simulators.… Read More
AMS Simulation Update from Mentor Graphics at DAC
I met with Jay Madiraju of Mentor Graphics on Wednesday at DAC to get an update on their AMS simulation products. We worked together at Mentor back when Mach TA was being developed as a Fast SPICE circuit simulator.… Read More


Intel to Compete with Broadcom and Marvell in the Lucrative ASIC Business