hip webinar automating integration workflow 800x100 (1)
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 3904
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 3904
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)
EDA

Electronic Design Automation

Posted on

EDA and ITC

EDA and ITC
by Daniel Payne on 10-17-2011 at 10:44 am
Categories: EDA, Synopsys

Every SOC that is designed must be tested and the premier conference for test is ITC, held last month in Anaheim, California.

I spoke with Robert Ruiz of Synopsys by phone on September 21st to get an update on what is new with EDA for test engineers this year. Robert and I first met back at Viewlogic when Sunrise was acquired in the 90’s.… Read More

Posted on

Soft IP Qualification

Soft IP Qualification
by Paul McLellan on 10-14-2011 at 3:10 pm
Categories: EDA

At the TSMC Open Innovation Platform Ecosystem Forum (try saying that three times in a row) next week (on Tuesday 18th), Atrenta will present a paper on the TSMC soft IP qualification flow. It will be presented by Anuj Kumar, senior manager of the customer consulting group.

More and more, chips are not put together what we think of … Read More

Posted on

FPGA Prototyping – What I learned at a Seminar

FPGA Prototyping – What I learned at a Seminar
by Daniel Payne on 10-14-2011 at 10:11 am
Categories: EDA, FPGA, Synopsys

Intro
My first exposure to hardware prototyping was at Intel back in 1980 when the iAPX 432 chip-set group decided to build a TTL-based wire-wrap prototype of a 32 bit processor to execute the Ada language. The effort to create the prototype took much longer than expected and was only functional a few months before silicon came back.… Read More

Posted on

A New Name: ‘Si2Con’ Arrives October 20th!

A New Name: ‘Si2Con’ Arrives October 20th!
by Daniel Nenni on 10-11-2011 at 7:58 pm
Categories: EDA, Semiconductor Services

In case you have not heard, the 16th Si2-hosted conference highlighting industry progress in design flow interoperability comes to Silicon Valley (Santa Clara, CA) on October 20th. Si2Con will showcase recent progress of members in the critical areas of:

[LIST=1]

  • Design tool flow integration (OpenAccess)
  • DRC / DFM / Parasitics
    • … Read More
    Posted on

    Mask and Optical Models–Evolution of Lithography Process Models, Part IV

    Mask and Optical Models–Evolution of Lithography Process Models, Part IV
    by Beth Martin on 10-10-2011 at 4:50 pm
    Categories: EDA, Siemens EDA

    Will Rogers said that an economist’s guess is liable to be as good as anyone’s, but with advanced-node optical lithography, I might have to disagree. Unlike the fickle economy, the distorting effects of the mask and lithographic system are ruled by physics, and so can be modeled.

    In this installment, I’ll talk about two critical… Read More

    Posted on

    Solido & TSMC Variation Webinar for Optimal Yield in Memory, Analog, Custom Digital Design

    Solido & TSMC Variation Webinar for Optimal Yield in Memory, Analog, Custom Digital Design
    by Daniel Nenni on 10-09-2011 at 4:01 pm
    Categories: EDA, Solido

    Solido has announced webinars for North America, Europe and Asia on October 12-13. They will be describing the variation analysis and design solutions in the TSMC AMS Reference Flow 2.0 announced at the Design Automation Conference this year.

    “We are pleased to broaden our collaboration with Solido in developing advanced variation… Read More

    Posted on

    How ST-Ericsson Improved DFM Closure using SmartFill

    How ST-Ericsson Improved DFM Closure using SmartFill
    by Daniel Payne on 10-07-2011 at 2:38 pm
    Categories: EDA, Siemens EDA

    DFM closure is a growing issue these days even at the 45nm node, and IC designers at ST-Ericsson have learned that transitioning from dummy fill to SmartFill has saved them time and improved their DFM score.

    The SOC
    ST-Ericsson designed an SOC for mobile platforms called the U8500 and their foundry choice was a 45nm node at STMicroelectronics… Read More

    Posted on

    Jasper User Group Meeting

    Jasper User Group Meeting
    by Paul McLellan on 10-07-2011 at 11:59 am
    Categories: EDA

    Jasper’s Annual User Group Meeting is on November 9th and 10th, in Cupertino California. It will feature users from all over the world sharing the best practices in verification. If you are a user of Jasper’s products then you should definitely plan to attend. This year there is so much good material that the meeting… Read More

    Posted on

    Testing, testing… 3D ICs

    Testing, testing… 3D ICs
    by Beth Martin on 10-06-2011 at 7:01 pm
    Categories: EDA, Siemens EDA

    3D ICs complicate silicon testing, but solutions exist now to many of the key challenges. – by Stephen Pateras

    The next phase of semiconductor designs will see the adoption of 3D IC packages, vertical stacks of multiple bare die connected directly though the silicon. Through-silicon vias (TSV) result in shorter and thinner… Read More

    Posted on

    Circuit Simulation and Ultra low-power IC Design at Toumaz

    Circuit Simulation and Ultra low-power IC Design at Toumaz
    by Daniel Payne on 10-06-2011 at 4:31 pm
    Categories: EDA

    I read about how Toumaz used the Analog Fast SPICE (AFS) tool from BDA and it sounded interesting so I setup a Skype call with Alan Wong in the UK last month to find out how they design their ultra low-power IC chips.


    Interview

    Q: Tell me about your IC design background.
    A: I’ve been at Toumaz almost 8 years now and before that at Sony… Read More