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Electronic Design Automation
We’re plagued by acronyms in this business. Wikipedia defines RTL as follows: “In digital circuit design, register-transfer level (RTL) is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those… Read More
What
In just 20 days you can get an update on four Mentor Graphics tools as used in the TSMC Open Innovation Platform (OIP). Many EDA and IP companies will be presenting along with Mentor, so it should be informative for fabless design companies in Silicon Valley doing business with TSMC.
… Read More
As described in DO-254, any inability to verify specific requirements by test on the device itself must be justified, and alternative means must be provided. Certification authorities favor verification by test for formal verification credits because of the simple fact that hardware flies not simulation models. Requirements… Read More
The Jasper User Group meeting has been announced. It will take place on November 12th and 13th. As last year, it will be at the Cypress Hotel at 10050 De Anza Boulevard in Cupertino. The user group meeting is free for qualified Jasper customers.
Topics to be covered are, of course, all things verification:
On Wednesday this week Ansys/Ansoft/Apache are presenting a new webinar Chip Aware System Design. It is presented by Dr Steven Gary Pytel Jr of the Ansoft part of Ansys, and Matt Elmore of the Apache subsidiary. The topics that will be covered include:
This is the 15[SUP]th[/SUP] anniversary for the SAME Conference, dedicated to innovation on Microelectronics. Sophia-Antipolis is not only close to Mediterranean sea, but also at the heart of Telecom valley in south of France, with Texas Instruments design center dedicated to Application Processor design (OMAP), Cadence… Read More
Yesterday I attended some of the Cadence mixed-signal technology summit. The day ended with a panel session on Are We Closing the Gap Yet in Mixed-signal Design? Richard Goering moderated. The panelists were all mixed signal experts:
What is the most read article on design on EE Times website? Brian Bailey has an article up running through the top 10. It turns out that the #1 article is Understanding Clock Domain Issues by Saurabh Verma and Ashima S. Dabare of Atrenta. It actually had more than double the views of the second place paper. Checking clock domain crossing… Read More
In this tough economy you may find yourself displaced and looking for the next opportunity. If you’d like to add some new EDA tool skills, then check out what EMA Design Automation is offering with free Cadence OrCAD training.… Read More
I have talked about Virtual Prototyping a SoC including FlexNoC Network on Chip IP from Arteris by using Carbon Design Systems set of tools in a previous post. A blog, posted on Carbon’ web, is clearly explaining the process to follow to optimize a fabric (FlexNoC) successively using the different tools from Carbon. Bill Neifert,… Read More
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Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot