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EDA

Electronic Design Automation

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Agilent ADS Users, Find Out About Design Data Management

Agilent ADS Users, Find Out About Design Data Management
by Paul McLellan on 06-20-2013 at 1:47 pm
Categories: Cliosoft, EDA

In May, ClioSoft and Agilent announced that Agilent’s Advanced Design System (ADS) was now integrated with ClioSoft’s SOS Design Data Management. I interviewed Greg Peterschmidt of Agilent at that time. The information page for the combined product, known as SOS viaADS is here.

 

Next week ClioSoft is presenting… Read More

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DAC by the Numbers

DAC by the Numbers
by Paul McLellan on 06-20-2013 at 12:03 pm
Categories: EDA, Events

The attendance numbers for DAC are out. Unless you have been living under a stone you know that DAC was in Austin Texas a couple of weeks ago. Attendance was:

  • full conference passes: 1589
  • exhibits-only passes: 2364
  • booth staff: 1998

The registration is slightly lower than last year when DAC was in San Francisco (as it will be again … Read More

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Static Low-Power Verification in Mixed-Signal SoC Designs

Static Low-Power Verification in Mixed-Signal SoC Designs
by Daniel Payne on 06-19-2013 at 2:02 pm
Categories: EDA

IC designer Shubhyant Chaturvediof AMD used EDA tools from Mentor Graphicsand Concept Engineeringto perform static, low-power verification of a mixed-signal SoC design with a combined CPU and GPU. Shubhyant presented a poster session at DAC two weeks ago in Austin, and I wanted to share it with my readers here at SemiWiki.… Read More

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A New STA Tool at DAC, No Not Cadence

A New STA Tool at DAC, No Not Cadence
by Daniel Payne on 06-19-2013 at 12:15 pm
Categories: EDA, Events

The big EDA companies get big attention at DAC, however sometimes the little EDA start-ups like Arcadia Innovationhave a new product that can be overlooked. On Tuesday at DAC I met with Joey Lin, founder of Arcadia Innovation and learned about his new STA (Static Timing Analysis) tool called TimeHawk .… Read More

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Deploying 14nm FinFETs in your Next Mobile SoC

Deploying 14nm FinFETs in your Next Mobile SoC
by Daniel Payne on 06-19-2013 at 11:05 am
Categories: EDA, FinFET, Foundries, GlobalFoundries, Synopsys

At DAC in Austin a design company, foundry and EDA vendor teamed up to present their experiences with 14nm FinFETs during a breakfast on Tuesday.

Panelists included:

… Read More
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Is Your Synchronizer Doing its Job (Part 1)?

Is Your Synchronizer Doing its Job (Part 1)?
by Jerry Cox on 06-18-2013 at 8:30 pm
Categories: EDA

Recently, I discussed the increasing risk of metastability hazards at nanoscale geometries. These risks are significantly aggravated at low supply voltages and low temperatures and must be addressed during the design cycle of any mission critical application. This time I discuss what it takes to estimate a synchronizer’s … Read More

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Derivative Designs Need Tools Too

Derivative Designs Need Tools Too
by Paul McLellan on 06-18-2013 at 11:58 am
Categories: EDA

Increasingly, SoC designs consist of assembling blocks of pre-designed IP. One special case is the derivative design where not just the IP blocks get re-used but a lot of the assembly itself. For example, in the design below some blocks are added, some blocks are updated, some hierarchy is changed. But the bulk of the design remains… Read More

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Increasing Automotive Semiconductor Test Quality

Increasing Automotive Semiconductor Test Quality
by glforte on 06-17-2013 at 4:45 pm
Categories: EDA, Siemens EDA

The growing amount of electronics within today’s automobiles is driving very high quality and reliability requirements to a widening range of semiconductor devices. At the same time, traditional fault models are becoming less effective at achieving desired silicon quality levels. Improvements in test solutions are needed… Read More

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Formality Ultra, Streamline Your ECOs

Formality Ultra, Streamline Your ECOs
by Paul McLellan on 06-17-2013 at 8:00 am
Categories: EDA, Synopsys

One of the most challenging stages in an SoC design is achieving timing closure. Actually design closure is perhaps a better term since everything needs to come together such as clock tree, power nets, power budget and so on. Changes made to the design are known as ECOs (which stands for engineering change orders, a term that comes… Read More