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EDA

Electronic Design Automation

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Validating Hard IP & Std Cell Libraries at DAC

Validating Hard IP & Std Cell Libraries at DAC
by Daniel Payne on 06-27-2013 at 3:13 pm
Categories: EDA, Fractal Technologies

The building blocks for every SoC are standard cell libraries that are assembled, designed and verified together. But how do we really know if all the data formats used during design are correct and consistent? To answer that question I spoke with Johan Peetersof Fractal Technologiesat DAC.


Johan Peeters, Rene Donkers
… Read More

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A 3D Field Solver for Parasitic Extraction Thermal ESD Analysis

A 3D Field Solver for Parasitic Extraction Thermal ESD Analysis
by Daniel Payne on 06-27-2013 at 2:38 pm
Categories: EDA, Events

The smaller the process node the more necessary it is that you extract accurate parasitics from interconnect and 3D structures in order to analyze timing, thermal effects and ESD compliance. Silicon Frontlinehas EDA tools in all three of these categories, so I met with Dermott Lynchat DAC to get an annual update.


Dermott Lynch,… Read More

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Aart: Technomic Push-Pull

Aart: Technomic Push-Pull
by Paul McLellan on 06-26-2013 at 11:00 pm
Categories: EDA, Synopsys

Aart de Geus gave one of the visionary look to the next 50 years of EDA as a warmup to Stephen Wu’s keynote. EDA is enabling the greatest push-pull ever, part of an exponential change on a scale never before seen.

Technologies seem to go through a 50 year technical push phase (driven by improving the technology) followed by a 50… Read More

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Kathryn Kranen: The Problem with EDA is…

Kathryn Kranen: The Problem with EDA is…
by Paul McLellan on 06-25-2013 at 5:35 pm
Categories: EDA

Kathryn Kranen, CEO of Jasper Design Automation, got to give her view of the future of EDA on the Thursday of DAC. For many years she has been on the EDAC board and is currently chair. When she first was on the board she talked to many of the stakeholders in the EDA ecosystem: EDA companies, IP companies, semiconductor companies, academics,… Read More

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Visual AMS Debug, an update at DAC

Visual AMS Debug, an update at DAC
by Daniel Payne on 06-24-2013 at 4:07 pm
Categories: Concept Engineering, EDA

If you’re involved with AMS or transistor-level IC design then having visual tools will help you design and debug quicker. At DAC I met with Gerhard Angst, President and Founder of Concept Engineering to get an update.


Gerhard Angst (center), Concept Engineering… Read More

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Full Visibility in ASIC Prototypes at DAC

Full Visibility in ASIC Prototypes at DAC
by Daniel Payne on 06-24-2013 at 3:46 pm
Categories: EDA, Tanner EDA

ASIC prototyping from multiple vendors using FPGA boards was popular at DAC again this year in Austin, Texas. I stopped by the Tektronix booth for a few minutes to meet with Dave Orecchio to get an update.


Dave Orecchio (right), Tektronix… Read More