Banner Electrical Verification The invisible bottleneck in IC design updated 1
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Formality Ultra, Streamline Your ECOs

Formality Ultra, Streamline Your ECOs
by Paul McLellan on 06-17-2013 at 8:00 am

One of the most challenging stages in an SoC design is achieving timing closure. Actually design closure is perhaps a better term since everything needs to come together such as clock tree, power nets, power budget and so on. Changes made to the design are known as ECOs (which stands for engineering change orders, a term that comes… Read More


Swap and Play Extended To Chip Fabric and Memory Controllers

Swap and Play Extended To Chip Fabric and Memory Controllers
by Paul McLellan on 06-16-2013 at 9:08 am

Virtual platforms enable software development to take place on a model of an electronic system. What everyone would like is models that are fast and accurate but that is simply not possible. Fast models are fast because they don’t model everything at the signal level. And accurate models get to be accurate by handling a lot of detail… Read More


GPU-Based SPICE Simulator for Library Characterization

GPU-Based SPICE Simulator for Library Characterization
by Daniel Payne on 06-13-2013 at 11:55 am

Jeff Tuanis the CEO and President of an EDA startup called G-Analog, founded in May 2012. His background includes working at: Cadence, Epic, Synopsys, Nassda, Chartered Semi and GLOBALFOUNDRIES. Jason Lu is the R&D manager. We met at DAC last week to talk about his company’s new product called Gchar for IC library characterization… Read More


Missed #50DAC? See Aldec Verification Sessions Online

Missed #50DAC? See Aldec Verification Sessions Online
by Daniel Nenni on 06-13-2013 at 12:00 am

Aldec, Inc. is an industry-leading Electronic Design Automation (EDA) company delivering innovative design creation, simulation and verification solutions to assist in the development of complex FPGA, ASIC, SoC and embedded system designs. With an active user community of over 35,000, 50+ global partners, offices worldwide… Read More


Increase Your Chip Reliability with iROC Tech

Increase Your Chip Reliability with iROC Tech
by Pawan Fangaria on 06-12-2013 at 9:00 pm

As we have moved towards extremely low process nodes with very high chip density, the cost of mask preparation also has become exorbitantly high. It has become essential to know about the failure rates and mitigate the same at the design time before chip fabrication, and also to make sure about chip reliability over time as it is constantly… Read More


So, where are all the EMBEDDED guys?

So, where are all the EMBEDDED guys?
by Don Dingee on 06-12-2013 at 8:15 pm

Roaming the aisles at #50DAC the past week left me with one unmistakable impression: there were two shows going on at the same time. Oh, we were all packed into one space together at the Austin Convention Center and neighboring hotels. But we weren’t quite all speaking the same language – yet.… Read More


Hardware Assisted Verification

Hardware Assisted Verification
by Paul McLellan on 06-10-2013 at 9:00 pm

On the Tuesday of DAC I moderated a panel session on Hardware Assisted Verification in 10 Years: More Need, More Speed. Although this topic obviously could include FPGA-based prototyping, in fact we spent pretty much the whole time talking about emulation. Gary Smith, on Sunday night, actually set up things by pointing out that… Read More


Custom Physical IC Design update from Cadence

Custom Physical IC Design update from Cadence
by Daniel Payne on 06-10-2013 at 8:05 pm

Custom IC design and layout is becoming more difficult at 20nm and smaller nodes, so the EDA tools have to get smarter and work harder for us in order to maintain productivity with the fewest iterations to reach our specs. Dave Stylesand John Stabenow of Cadence met with me last Monday in Austin at the DAC exhibit area.


John StabenowRead More