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Converge in Detroit

Converge in Detroit
by Paul McLellan on 09-30-2012 at 10:04 pm

When I worked for VaST we went to a show that I’d never heard of in EDA: SAE Convergence (SAE is the Society of Automotive Engineers). It is held once every two years and it focuses on transportation electronics, primarily automotive although there did seem to be some aerospace stuff there too. This is an even year, Convergence… Read More


A Brief History of RTL Design

A Brief History of RTL Design
by Daniel Payne on 09-27-2012 at 9:00 pm

300px Register transfer level   example toggler.svg

RTL is an acronym for Register Transfer Level and refers to a level of hardware design abstraction using Registers and logic gates. Here’s an example schematic showing one DFF as a register, and one inverter as a logic gate.


Figure 1: RTL diagram of a DFF (D Flip Flop) and InverterRead More


Variation at 28-nm with Solido and GLOBALFOUNDRIES

Variation at 28-nm with Solido and GLOBALFOUNDRIES
by Kris Breen on 09-27-2012 at 9:00 pm

At DAC 2012 GLOBALFOUNDRIES and Solido presented a user track poster titled “Understanding and Designing for Variation in GLOBALFOUNDRIES 28-nm Technology” (as was previously announced here). This post describes the work that we presented.

We set out to better understand the effects of variation on design at 28-nm. In particular,… Read More


A Brief History of Atrenta and RTL Design

A Brief History of Atrenta and RTL Design
by Daniel Nenni on 09-26-2012 at 7:41 pm

We’re plagued by acronyms in this business. Wikipedia defines RTL as follows: “In digital circuit design, register-transfer level (RTL) is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those… Read More


Mentor Graphics Update at TSMC 2012 OIP

Mentor Graphics Update at TSMC 2012 OIP
by Daniel Payne on 09-26-2012 at 10:45 am

What
In just 20 days you can get an update on four Mentor Graphics tools as used in the TSMC Open Innovation Platform (OIP). Many EDA and IP companies will be presenting along with Mentor, so it should be informative for fabless design companies in Silicon Valley doing business with TSMC.
Read More


Aldec-Altera DO-254

Aldec-Altera DO-254
by Daniel Nenni on 09-25-2012 at 9:58 pm

As described in DO-254, any inability to verify specific requirements by test on the device itself must be justified, and alternative means must be provided. Certification authorities favor verification by test for formal verification credits because of the simple fact that hardware flies not simulation models. RequirementsRead More


Jasper User Group

Jasper User Group
by Paul McLellan on 09-25-2012 at 1:19 pm

The Jasper User Group meeting has been announced. It will take place on November 12th and 13th. As last year, it will be at the Cypress Hotel at 10050 De Anza Boulevard in Cupertino. The user group meeting is free for qualified Jasper customers.

Topics to be covered are, of course, all things verification:

  • SoC subsystems verification
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Chip Aware System Design

Chip Aware System Design
by Paul McLellan on 09-24-2012 at 5:45 pm

On Wednesday this week Ansys/Ansoft/Apache are presenting a new webinar Chip Aware System Design. It is presented by Dr Steven Gary Pytel Jr of the Ansoft part of Ansys, and Matt Elmore of the Apache subsidiary. The topics that will be covered include:

  • Power Delivery Network (PDN) design requirements
  • ABCD Matrix theory
  • SYZ Matrix
Read More

SAME 2012 Conference on October 2-3 in Sophia is coming soon!

SAME 2012 Conference on October 2-3 in Sophia is coming soon!
by Eric Esteve on 09-24-2012 at 11:01 am

This is the 15[SUP]th[/SUP] anniversary for the SAME Conference, dedicated to innovation on Microelectronics. Sophia-Antipolis is not only close to Mediterranean sea, but also at the heart of Telecom valley in south of France, with Texas Instruments design center dedicated to Application Processor design (OMAP), Cadence… Read More


Cadence Mixed Signal Technology Summit

Cadence Mixed Signal Technology Summit
by Paul McLellan on 09-21-2012 at 6:46 pm

Yesterday I attended some of the Cadence mixed-signal technology summit. The day ended with a panel session on Are We Closing the Gap Yet in Mixed-signal Design? Richard Goering moderated. The panelists were all mixed signal experts:

  • Nayaz Khan of Maxim
  • Nishant Shah of Broadcom
  • Shiv Sikand of IC Manage
  • Bill Meier of Texas Instruments
Read More