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Kathryn Kranen: The Problem with EDA is…

Kathryn Kranen: The Problem with EDA is…
by Paul McLellan on 06-25-2013 at 5:35 pm

Kathryn Kranen, CEO of Jasper Design Automation, got to give her view of the future of EDA on the Thursday of DAC. For many years she has been on the EDAC board and is currently chair. When she first was on the board she talked to many of the stakeholders in the EDA ecosystem: EDA companies, IP companies, semiconductor companies, academics,… Read More


Visual AMS Debug, an update at DAC

Visual AMS Debug, an update at DAC
by Daniel Payne on 06-24-2013 at 4:07 pm

If you’re involved with AMS or transistor-level IC design then having visual tools will help you design and debug quicker. At DAC I met with Gerhard Angst, President and Founder of Concept Engineering to get an update.


Gerhard Angst (center), Concept EngineeringRead More


Full Visibility in ASIC Prototypes at DAC

Full Visibility in ASIC Prototypes at DAC
by Daniel Payne on 06-24-2013 at 3:46 pm

ASIC prototyping from multiple vendors using FPGA boards was popular at DAC again this year in Austin, Texas. I stopped by the Tektronix booth for a few minutes to meet with Dave Orecchio to get an update.


Dave Orecchio (right), TektronixRead More


Fujitsu, Mediatek, Richtek and Synopsys om Custom IC Design

Fujitsu, Mediatek, Richtek and Synopsys om Custom IC Design
by Daniel Payne on 06-24-2013 at 3:01 pm

Synopsys has been acquiring EDA and IP companies at a fast clip over the past few years and it’s often made me wonder how they are going to craft a coherent tool flow for custom IC design. At DACthis year I learned that for schematic capture the winning tool is Custom Designer SE– a relatively new tool, while the IC layout… Read More


Is Your Synchronizer Doing its Job (Part 2)?

Is Your Synchronizer Doing its Job (Part 2)?
by Jerry Cox on 06-23-2013 at 8:10 pm

In Part 1 of this topic I discussed what it takes to estimate the mean time between failures (MTBF) of a single stage synchronizer. Because supply voltages are decreasing and transistor thresholds have been pushed up to minimize leakage, the shortened MTBF of many synchronizer circuits at nanoscale process nodes is presenting… Read More


Pat Pistilli: the first cell library, the first computer-printed label and more

Pat Pistilli: the first cell library, the first computer-printed label and more
by Paul McLellan on 06-22-2013 at 1:45 pm

At the DAC 50th anniversary banquet, Pat Pistilli won the award for most tenacious attendee, having been to all 50 DACs. Well, and for creating DAC and sustaining it. He was general chair for the first DAC (not yet called DAC) and, of course, would eventually form MP Associates with his wife Marie, which still runs DAC today. In 2010… Read More


Can we really find a way to speed-up Processor & DSP core designs?

Can we really find a way to speed-up Processor & DSP core designs?
by Eric Esteve on 06-21-2013 at 9:05 am

Once upon a time, ASIC designers involved in Processor design, like I was, for the first time in 1987 for Thomson CSF and again in 1994 for Texas Instruments, at that time supporting height (8) ASIC designed by another French company, the Advanced Computer Research Institute (ACRI), had to re-invent the wheel almost every day. When… Read More


Agilent ADS Users, Find Out About Design Data Management

Agilent ADS Users, Find Out About Design Data Management
by Paul McLellan on 06-20-2013 at 1:47 pm

In May, ClioSoft and Agilent announced that Agilent’s Advanced Design System (ADS) was now integrated with ClioSoft’s SOS Design Data Management. I interviewed Greg Peterschmidt of Agilent at that time. The information page for the combined product, known as SOS viaADS is here.

 

Next week ClioSoft is presenting… Read More