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EDA

Electronic Design Automation

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Synopsys Creates a High-performance ARC Core

Synopsys Creates a High-performance ARC Core
by Paul McLellan on 11-05-2013 at 10:00 am
Categories: IP, Synopsys

ARC is a family of configurable processors. Originally it was a standalone company in the UK (what is it with the UK and processor cores?) spun out from Argonaut Software. The A in ARC stood for Argonaut originally. ARC International was acquired by Virage and then Virage was acquired by Synopsys so now it is part of Synopsys Designware… Read More

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Addressing Power at Architectural and RTL Levels

Addressing Power at Architectural and RTL Levels
by Paul McLellan on 11-03-2013 at 4:30 pm
Categories: EDA

Major power reductions are possible by reducing power at the RTL and system levels, and not just at the gate and physical level. In fact, as is so often the case in design, changes can have much more impact when done at the higher level, even given that at that point in the design there is less accurate feedback about changes. Later the… Read More

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Fabless: The Transformation of the Semiconductor Industry

Fabless: The Transformation of the Semiconductor Industry
by Daniel Nenni on 11-03-2013 at 4:00 pm
Categories: EDA, Foundries, IP


As I have mentioned before, Paul McLellan and I are writing a book on the history of the fabless semiconductor industry. There is a preview available HERE, it will initially be sold as an e-book on SemiWiki and put into print early next year. Working with Paul McLellan and Beth Martin on this was an amazing experience. The research,… Read More

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Webinar: IP Lifecycle Management: What is it, what problems does it solve?

Webinar: IP Lifecycle Management: What is it, what problems does it solve?
by Daniel Nenni on 11-03-2013 at 11:00 am
Categories: EDA, Perforce

SoC’s are now dominated by IP blocks sourced either from 3rd parties or internal design teams. This means that IP is now critical to the success of the SoC, yet it is part of the design that teams have the least control over, or visibility into. Most design teams utilize at best ad-hoc methods to manage this IP, and the few that utilize… Read More

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Using Formal to Find Bugs in ARM Microprocessors

Using Formal to Find Bugs in ARM Microprocessors
by Paul McLellan on 11-01-2013 at 12:35 am
Categories: EDA

2.5x ROI vs simulation. 25% of bugs found for only 10% of the overall verification cost. 36% of bugs in a current CPU project. These impressive results for formal analysis are what ARM’s Laurent Arditi reported at JUG 2013 after painstaking recording of metrics over several production programs.


As you can see from the above graph,… Read More

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I could show you the FPGA, but then I’d have to configure you

I could show you the FPGA, but then I’d have to configure you
by Don Dingee on 10-31-2013 at 6:00 pm
Categories: Aldec, EDA, FPGA

One of the present ironies of the Internet of Things is as it seeks to connect every device on the planet, we are still designing those things with largely unconnected EDA tools. We may share libraries and source files on a server somewhere, but that is just the beginning of connection.

It is not surprising that synthesis tools from… Read More

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Device Noise Analysis of Switched-Cap Circuits

Device Noise Analysis of Switched-Cap Circuits
by Daniel Payne on 10-31-2013 at 12:00 pm
Categories: EDA

Switched-capacitor circuits are used in most CMOS mixed-signal ICs as:

  • Track and hold circuits
  • Integrators
  • Operational Amplifiers
  • Delta-sigma modulators


​Delta-Sigma Modulator: IEEE J. Solid-State Circuits, vol. 43, no. 12, pp 2601-2612, Dec. 2008… Read More

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M-PCIe, Data Converters, and USB 3.0 SSIC at IP SoC 2013

M-PCIe, Data Converters, and USB 3.0 SSIC at IP SoC 2013
by Eric Esteve on 10-31-2013 at 9:38 am
Categories: EDA, Synopsys

Synopsys is taking IP-SOC 2013 seriously, as the company will hold several presentations, starting with a Keynote: “Virtual Prototyping – A Reality Check”, by Johannes Stahl, Director, Product Marketing, System-Level Solutions, Synopsys, highlighting current industry practice around putting virtual prototyping to work… Read More

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ARM in Samsung 14nm FinFET

ARM in Samsung 14nm FinFET
by Paul McLellan on 10-30-2013 at 4:28 pm
Categories: Arm, Cadence, EDA, Foundries, Samsung Foundry

I am at ARM TechCon today. One interesting presentation was made jointly between Samsung, Cadence and ARM themselves about developing physical libraries (ARM), a tool flow (Cadence) and test chips (Samsung). It was titled Samsung ARM and Cadence collaborate on the silicon-proven world first 14-nm FinFET Cortex-A7 ARM CPU and… Read More

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ARC EM SEP Processor, Safety Ready Solution for Automotive

ARC EM SEP Processor, Safety Ready Solution for Automotive
by Eric Esteve on 10-30-2013 at 5:24 am
Categories: EDA, Synopsys

If you are familiar with Processor IP core, you certainly know DesignWare ARC EM4 core, 32-bit CPU that SoC designers can optimize for a wide range of uses, and differentiate by using patented configuration technology to tailor each ARC core instance to meet specific performance, power and area requirements. If you develop a product… Read More