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EDA

Electronic Design Automation

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Atrenta Seminars in Asia – Making RTL Signoff Real

Atrenta Seminars in Asia – Making RTL Signoff Real
by Daniel Nenni on 08-18-2013 at 8:10 pm
Categories: EDA

Engaging with the semiconductor ecosystem is critical to surviving in the fast paced times we work in. Face to face interaction at all levels is key and semiconductor IP is a prime example. How do you ensure that your IP meets objective quality requirements before integration into your SoC, and that your SoC is ready for handoff to… Read More

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Why Adopt Hierarchical Test for SoC Designs

Why Adopt Hierarchical Test for SoC Designs
by Daniel Payne on 08-15-2013 at 4:37 pm
Categories: EDA, Synopsys, TSMC

IC designers have been creating with hierarchy for years to better manage large design sizes, however for the test world the concept of hierarchy and emerging standards is a bit newer. TSMC and Synopsys jointly created a webinarthat addresses hierarchical test, so I’ve attended it this week and summarized my findings here.… Read More

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Accelerating SoC Simulation Times

Accelerating SoC Simulation Times
by Daniel Payne on 08-15-2013 at 2:43 pm
Categories: Aldec, EDA, FPGA

There never seems to be enough time in a SoC project to simulate all of the cycles and tests that you want to run, so any technique to accelerate each run is welcomed. You can just wait for your software-based RTL simulator to finish running, or you can consider using a hardware-based accelerator approach. I learned more about one such… Read More

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Don’t Shoot Yourself in the Foot With Timing Exceptions

Don’t Shoot Yourself in the Foot With Timing Exceptions
by Paul McLellan on 08-15-2013 at 1:42 pm
Categories: EDA

Timing exceptions are ways of guiding design tools, primarily synthesis and static timing analysis (STA), but these days also place & route and perhaps other tools. Most paths in a design go from one register to the next register. Both registers are on the same clock, and the design needs to ensure that the signal can make it from… Read More

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Let’s Drive To Dearborn on 19th Sep….

Let’s Drive To Dearborn on 19th Sep….
by Pawan Fangaria on 08-15-2013 at 11:00 am
Categories: EDA, Siemens EDA


[The VLC developed by Edison2, winner of the Progressive Automotive X-Prize]

Now that we have “The Very Light Car” of the world at more than 100 MPG!! Yes, this is the car developed by Edison2, one among the three winners of the Progressive Insurance Automotive X-Prize, a global competition; Edison2 won in the main stream class. … Read More

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How to Benchmark a Processor

How to Benchmark a Processor
by Paul McLellan on 08-15-2013 at 2:11 am
Categories: Arm, Imagination Technologies, IP, Synopsys

How do you benchmark a processor? It seems like it should be easy, just run some code and see how fast it is. Traditionally processors were indeed benchmarked by raw performance like GMACS, GFLOPS, memory bandwidth and so on. But in today’s world where systems have become very complex and applications very compute intensive, the… Read More

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Happy Birthday Dear Cadence…

Happy Birthday Dear Cadence…
by Paul McLellan on 08-14-2013 at 8:30 pm
Categories: Cadence, EDA

Cadence is 25 years old this year, on June 1st if you want to be precise.

The most direct ancestor of Cadence was SDA (which might or might not have stood for Solomon Design Automation). SDA was founded by Jim Solomon in 1983. It turns out that a guy I shared an office with while we were both doing our PhDs in Edinburgh Scotland was one of … Read More

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An EDA Acquisition that Worked

An EDA Acquisition that Worked
by Daniel Payne on 08-14-2013 at 5:30 pm
Categories: Ansys, Inc., EDA

I first heard about Andrew Yang back in 1993 when he founded a Fast SPICE company called Anagram, then acquired by Avant! in 1996. Andrew’s latest EDA company Apache Design, Inc.was started in 2001, then acquired by ANSYS in 2011. Most EDA mergers simply don’t work because of one or more reasons, like:

  • Incompatible
… Read More
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How Resistant to Neutrons Are Your Storage Elements?

How Resistant to Neutrons Are Your Storage Elements?
by Paul McLellan on 08-13-2013 at 1:01 pm
Categories: EDA, IROC Technologies

There are two ways to see how resistant your designs are to single-event errors (SEE). One is to take the chip or even the entire system and put it in a neutron beam and measure how many problems occur in this extreme environment. While that may be a necessary part of qualification in some very high reliability situations, it is also … Read More

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Electronic System Level: Gary Smith

Electronic System Level: Gary Smith
by Paul McLellan on 08-12-2013 at 5:07 pm
Categories: EDA

Gary Smith has been talking about how the electronic system level (ESL) is where the future of EDA lies as design teams move up to higher levels encompassing IP blocks, high level synthesis, software development using virtual platforms and so on. At DAC this year in Austin he talked about how the fact that EDA controls the modeling… Read More