CAST Compression IP Webinar 800x100 (2)
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4178
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4178
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)
EDA

Electronic Design Automation

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Test Compression and Hierarchy at ITC

Test Compression and Hierarchy at ITC
by Daniel Payne on 09-09-2013 at 8:00 am
Categories: EDA, Synopsys

The International Test Conference (ITC) is this week in Anaheim and I’ve just learned what’s new at Synopsys with test compression and hierarchy. Last week I spoke with Robert Ruiz and Sandeep Kaushik of Synopsys by phone to get the latest scoop. There are two big product announcements today that cover:… Read More

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Xilinx At 28nm: Keeping Power Down

Xilinx At 28nm: Keeping Power Down
by Paul McLellan on 09-08-2013 at 2:26 pm
Categories: Ansys, Inc., FPGA, TSMC, Xilinx

Almost without exception these days, semiconductor products face strict power and thermal budgets. Of course there are many issues with dynamic power but one big area that has been getting increasingly problematic is static power. For various technical reasons we can no longer reduce the voltage as much as we would like from one… Read More

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Asian Embargoes

Asian Embargoes
by Paul McLellan on 09-07-2013 at 8:00 pm
Categories: EDA

[This blog embargoed until 10am China time]

An interesting thing happened to me this week. I had two press briefings. No, that wasn’t the interesting thing and if you have sat through a press briefing you will not regard them as recreation. I do it for you, Semiwiki readers. Even though, as this week, the briefings are given … Read More

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SpyGlass: Focusing on Test

SpyGlass: Focusing on Test
by Paul McLellan on 09-07-2013 at 5:51 pm
Categories: EDA

For decades we have used a model of faults in chips that assumes that a given signal is stuck-at-0 or stuck-at-1. And when I say decades, I mean it. The D-algorithm was invented at IBM in 1966, the year after Gordon Moore made a now very famous observation about the number of transistors on an integrated circuit. We know that stuck-at… Read More

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Did you miss Cadence’s MemCon?

Did you miss Cadence’s MemCon?
by Eric Esteve on 09-05-2013 at 4:42 am
Categories: Cadence, IP

That’s too bad, as you have missed latest news about the Hybrid Memory Cube (presentation by Micron), Wide I/O 2 standard, as well as other standards like LPDDR4, eMMC 5.0, and LRDIMM,the good news is that you may find all these presentations on MemCon proceedings web site.
I first had a look at Richard Goering excellent blog: wideI/O… Read More

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Real Time Concurrent Layout Editing – It’s Possible

Real Time Concurrent Layout Editing – It’s Possible
by Pawan Fangaria on 09-03-2013 at 2:00 pm
Categories: EDA, Siemens EDA

Layout editing is a complex task, traditionally done manually by designers, and the layout design productivity largely depends on the designer’s skills and expertise. However, a good tool with features for ease of design is a must. Layout productivity has been an area of focus and various features are constantly being added in… Read More

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Low-Power Design Webinar – What I Learned

Low-Power Design Webinar – What I Learned
by Daniel Payne on 09-02-2013 at 7:00 pm
Categories: Ansys, Inc., EDA

You can only design and optimize for low-power SoC designs if you can actually simulate the entire Chip, Package and System together. The engineers at ANSYS-Apachehave figured out how to do that and talked about their design for power methodology in a webinar today. I listened to Arvind Shanmugavel present a few dozen slides and… Read More

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Analog ECOs and Design Reviews: How to Do Them Better

Analog ECOs and Design Reviews: How to Do Them Better
by Paul McLellan on 09-02-2013 at 1:00 am
Categories: Cliosoft, EDA

One of the challenges in doing a complex analog or mixed signal design is that things get out of step. One designer is tweaking the schematic and re-simulating, another is tweaking the layout of transistors, another is changing the routing. This is not because the design flow is messed up, but rather it reflects reality. If you wait… Read More

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Reliability sign-off has several aspects – One Solution

Reliability sign-off has several aspects – One Solution
by Pawan Fangaria on 09-01-2013 at 5:00 pm
Categories: Ansys, Inc., EDA

Here, I am talking about reliability of chip design in the context of electrical effects, not external factors like cosmic rays. So, the electrical factors that could affect reliability of chips could be excessive power dissipation, noise, EM (Electromigration), ESD (Electrostatic Discharge), substrate noise coupling and… Read More

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It’s a 14nm photomask, what could possibly go wrong?

It’s a 14nm photomask, what could possibly go wrong?
by Don Dingee on 08-27-2013 at 3:16 pm
Categories: EDA, Siemens EDA

Let’s start with the bottom line: in 14nm processes, errors which have typically been little more than noise with respect to photomask critical dimension (CD) control targets at larger process nodes are about to become very significant, even out of control if not accounted for.… Read More