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The Most Popular Blog Posts at Cadence in 2013

The Most Popular Blog Posts at Cadence in 2013
by Daniel Payne on 12-19-2013 at 11:42 am

I spend about an hour a day reading blogs from EDA companies, foundries, independent bloggers and of course, SemiWiki. Richard Goering at Cadence assembled a top 10 list of the most popular blogs posted on their site in 2013, revealing that engineers were most interested in: FinFETs, 20nm and smaller nodes, memory technology and… Read More


Complete IP port-folio built in less than two years!

Complete IP port-folio built in less than two years!
by Eric Esteve on 12-18-2013 at 10:47 am

We have posted several blogs related to Cadence IP strategy, or I should say new strategy. Each of these blogs was dealing with a particular product, like PCI Express gen-3 Controller IP, latest DDR4 Memory Controller or Wide I/O. This approach was equivalent to describe trees, one after one, and finally ignoring the forest! It’s… Read More


DAC 2014: Designer Track/IP Call for Submissions

DAC 2014: Designer Track/IP Call for Submissions
by Daniel Nenni on 12-17-2013 at 8:00 pm

Yes, it is that time of year again, DAC is coming and it is in San Francisco so you can bet we will break attendance records, absolutely. I would like to call on ALL semiconductor IP companies to exhibit this year. IP is the center of the semiconductor design universe, DAC is the premier semiconductor design event, and San Francisco … Read More


Happy Holidays from Atrenta

Happy Holidays from Atrenta
by Paul McLellan on 12-17-2013 at 7:51 pm

It is that time of year and once again Atrenta has produced a video wishing you all the best for the holiday season. They are so spread around the world it is not just Hanukkah and Christmas but the Asian Lunar New Year (end of January) and probably some more holidays I don’t even know about. Last year there was a competition to name… Read More


Security Path Verification

Security Path Verification
by Paul McLellan on 12-16-2013 at 5:18 pm

Formal approaches and security are a perfect match since you really want to prove that there are no holes in your security, rather than just being fairly confident. At the recent Jasper User Group meeting, Victor Purri presented some case studies in security verification.

The Jasper Security Path Verification (SPV) App is used… Read More


Why integrating HDMI 2.0?

Why integrating HDMI 2.0?
by Eric Esteve on 12-16-2013 at 8:47 am

High Definition Multimedia Interface (HDMI) is today part of our day to day life, at home as well as at our office we are using devices integrating HDMI ports. HDMI penetration is well illustrated by this picture (created in Dec. 2011 by In-Stat): from DTV to Game console, the devices belong to the Consumer Electronics market segments,… Read More


Mentor Buys Oasys

Mentor Buys Oasys
by Paul McLellan on 12-14-2013 at 1:24 pm

Mentor is acquiring Oasys, subject to all the usual caveats about shareholder and regulatory approval. The shareholder paperwork went out earlier this week. The common stock is valueless so presumably the price is low (and Mentor historically has not paid high prices for its acquisitions).

So what is going to happen with the technology?… Read More


Verification of Multirate Systems with Multiple Digital Blocks

Verification of Multirate Systems with Multiple Digital Blocks
by Daniel Payne on 12-13-2013 at 8:27 pm

Our popular smart phones have a whole slew of RF-based radios in them for: Bluetooth, WiFi, LTE, GSM, NFC. Using just a single clock frequency for a DSP function or SoC is a thing of the past, so the design of multirate systems is here to stay. So now the challenge on the design and verification side is to use a methodology that supports:… Read More


AMD Goes 3D

AMD Goes 3D
by Paul McLellan on 12-13-2013 at 7:16 pm

I attended the 3D packaging conference in Burlingame this week. The most interesting presentation to me was by Bryan Black of AMD. He argued very convincingly that Moore’s Law is basically over for the PC microprocessor business and the way forward is going to be 3D. AMD are clearly working on all this.

Increased density and… Read More


Taming The Interconnect In Real World For SoCs

Taming The Interconnect In Real World For SoCs
by Pawan Fangaria on 12-13-2013 at 1:30 pm

Interconnect plays a significant role in the semiconductor design of a SoC; if not architected and handled well, it can lead to an overdesigned SoC impacting on its power, performance and area. Since a SoC generally contains multiple IPs requiring different data paths to satisfy varying latency and performance cycles, it has … Read More