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Parasitic Debugging in Complex Design – How Easy?

Parasitic Debugging in Complex Design – How Easy?
by Pawan Fangaria on 01-23-2014 at 9:00 am

When we talk about parasitic, we talk about post layout design further expanded in terms of electrical components such as resistances and capacitances. In the semiconductor design environment where multiple parts of a design from different sources are assembled together into highly complex, high density SoC, imagine how complex… Read More


ESD at TSMC: IP Providers Will Need to Use Mentor to Check

ESD at TSMC: IP Providers Will Need to Use Mentor to Check
by Paul McLellan on 01-22-2014 at 1:24 pm

I met with Tom Quan of TSMC and Michael Beuler-Garcia of Mentor last week. Weirdly, Mentor’s newish buildings are the old Avant! buildings where I worked for a few weeks after selling Compass Design Automation to them. Odd sort of déja vu. Historically, TSMC has operated with EDA companies in a fairly structured way: TSMC … Read More


Have you Tried ALDEC?

Have you Tried ALDEC?
by Luke Miller on 01-22-2014 at 1:00 pm

I must admit. I was too comfortable. Let me explain, I’m a ModelSim guy from Mentor Graphics. I did not really think nor care much of the other RTL simulator options. How could someone build a better tool with respect to simulation? Let me introduce you to Aldec. Aldec was founded in 1984 by Dr. Stanley M. Hyduke. 30 years later they are… Read More


Just Released! Fabless: The Transformation of the Semiconductor Industry

Just Released! Fabless: The Transformation of the Semiconductor Industry
by Daniel Nenni on 01-22-2014 at 12:00 pm

The book “Fabless: The Transformation of the Semiconductor Industry” is now available in the Kindle (mobi) and iBooks (ePub) formats. We are really looking forward to your feedback before we go to print in March. This was truly a Tom Sawyer experience for me. As the story goes Tom made whitewashing a fence seem like fun so his friends… Read More


A Power Optimization Flow at the RTL Design Stage

A Power Optimization Flow at the RTL Design Stage
by Daniel Payne on 01-21-2014 at 10:20 pm

SoC designers can code RTL, run logic synthesis, perform place and route, extract the interconnect, then simulate to measure power values. Though this approach is very accurate, it’s also very late in the implementation flow to start thinking about how to actually optimize a design for the lowest power while meeting all… Read More


Semiconductor IP and Correct-by-construction Workspaces

Semiconductor IP and Correct-by-construction Workspaces
by Daniel Payne on 01-21-2014 at 8:00 pm

SoC hardware designers could learn a thing or two from the world of software development, especially when it comes to the topic of managing complexity. Does that mean that hardware designers should literally use a software development environment, and force fit hardware design into file and class-based software methodologies?… Read More


Smart Clock Gating for Meaningful Power Saving

Smart Clock Gating for Meaningful Power Saving
by Pawan Fangaria on 01-21-2014 at 5:30 am

Since power has acquired a prime spot in SoCs catering to smart electronics performing multiple jobs at highest speed; the semiconductor design community is hard pressed to find various avenues to reduce power consumption without affecting functionality and performance. And most of the chips are driven by multiple clocks that… Read More


Digital @ Nano-Scale while Analog Hovers @ 65nm and Above

Digital @ Nano-Scale while Analog Hovers @ 65nm and Above
by Daniel Nenni on 01-20-2014 at 9:00 pm

Who’s going to DesignCon next week? I am, absolutely. Dr. Hermann Eul, Vice President & General Manager, Mobile & Communications Group, Intel Corporation will be keynoting on Tuesday. This one I want to hear! Intel missed mobile at 32nm, 22nm, and 14nm. Lets see what they have planned for 10nm. Something good I hope!… Read More


The Semiconductor Landscape – III

The Semiconductor Landscape – III
by Pawan Fangaria on 01-20-2014 at 12:30 pm

In continuation to my earlier observations and anticipations (landscape1, landscape2) which came up to my expectations, I was further inspired to ponder over the macros of our ever growing semiconductor industry. We may argue the business is stagnating, we may argue that the pace of scaling is slowing, but when I look back at the… Read More


Managing Heat for System Reliability

Managing Heat for System Reliability
by Pawan Fangaria on 01-17-2014 at 8:30 am

In most of the electronic equipments, semiconductor chips are a major source of heat generation. And in semiconductor designs several hardware and software techniques are being used to contain power dissipation; a major cause for heat. However due to multiple functionality being squeezed into small form factors, we continue… Read More