Banner Electrical Verification The invisible bottleneck in IC design updated 1
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EDA

Electronic Design Automation

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Synopsys Acquires Coverity

Synopsys Acquires Coverity
by Paul McLellan on 02-19-2014 at 5:27 pm
Categories: EDA, Synopsys

Synopsys announced this afternoon that they are acquiring Coverity for $375M subject to all the usual reviews.

There are a couple of other big EDA connections. Aki Fujimora, who was CTO of Cadence, is on the board. And Adreas Kuehlmann is the VP of R&D. He used to run Cadence Berkeley Laboratories before moving to the other end… Read More

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One SPIE session not to miss

One SPIE session not to miss
by Beth Martin on 02-19-2014 at 4:19 pm
Categories: EDA, Siemens EDA

The time is nigh for another meeting of the practitioners of the lithographic arts, dark and otherwise, at the SPIE Advanced Lithography symposium.

I love this conference for the engagement you see, both in the sessions and in the hallways. People actually meet and talk and argue. There’s always interesting gossip, exciting technologies,… Read More

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Carbon Design Systems – Secret of Success

Carbon Design Systems – Secret of Success
by Pawan Fangaria on 02-19-2014 at 11:00 am
Categories: EDA


Last week, after learning from the press releaseof Carbonabout its rocking sustained growth with record-breaking revenue and a thumping 46% increase in bookings, I was interested to know some more details about what drives Carbon to such an amazing performance in an EDA market that is generally prone to growth of a few percentage… Read More

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Verifying DRC Decks and Design Rule Specifications

Verifying DRC Decks and Design Rule Specifications
by Daniel Nenni on 02-19-2014 at 8:00 am
Categories: EDA, Sage DA

DRVerify is part of the iDRM design rule compiler platform from Sage DA, something that I have been personally involved with for the past three years. DRVerify is mainly used to verify third party design rule check (DRC) decks and ensure that they correctly, completely and accurately represent the design rule specification. In… Read More

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Verification of Power Delivery Networks

Verification of Power Delivery Networks
by Paul McLellan on 02-18-2014 at 2:43 pm
Categories: EDA, Siemens EDA

Power delivery networks (PDN) are the metal structures on a chip that delivers the power. In a high-end desktop SoC this might be delivering as much as 150W, and with voltages around 1V that means over 150 amps of current. Clearly getting the PDN correct is critical for a correctly functioning chip. One of the challenges to verifying… Read More

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HDMI, DisplayPort, MHL IPs + Engineering Team = Good Move

HDMI, DisplayPort, MHL IPs + Engineering Team = Good Move
by Eric Esteve on 02-17-2014 at 10:18 am
Categories: Cadence, IP

This news is certainly not as amazing that the acquisition of MIPS by Imagination, or Arteris by Qualcomm… but it shows that Cadence is building a complete Interface IP port-folio, brick after brick. The result will be that a complete wall is being built on the Synopsys road to monopoly and complete success on Interface IP market.… Read More

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Speeding Up AMS Verification by Modeling with Real Numbers

Speeding Up AMS Verification by Modeling with Real Numbers
by Daniel Payne on 02-15-2014 at 7:00 pm
Categories: Siemens EDA

My first introduction to modeling an AMS behavior using a language was back in the 1980’s at Silicon Compilers using the Lsim simulator. Around the same time the VHDL and Verilog languages emerged to handle the modeling of both digital and some analog behaviors. The big reason to model analog behavior with a language is for… Read More

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I switched to Aldec Active-HDL

I switched to Aldec Active-HDL
by Luke Miller on 02-12-2014 at 3:00 pm
Categories: Aldec, EDA

I have written this before, but I was a ModelSim snob. That has changed after trying Active-HDL from Aldec. I have no plans on going back to ModelSim. You ask why? Well astute reader, great question. Unfortunately these blogs are text limited and there is no way to write about all the bells and whistles of Active-HDL. So before I continue,… Read More

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Smart Strategies for Efficient Testing of 3D-ICs

Smart Strategies for Efficient Testing of 3D-ICs
by Pawan Fangaria on 02-12-2014 at 6:30 am
Categories: EDA, Siemens EDA

3D-IC has a stack of dies connected and packaged together, and therefore needs new testing strategies other than testing a single die. It’s given that a single defective die can render the whole of 3D-IC unusable, so each die in the stack must be completely and perfectly tested before its entry into that stack. Looking at it from a … Read More

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Designing an SoC with 16nm FinFET

Designing an SoC with 16nm FinFET
by Daniel Payne on 02-11-2014 at 9:35 pm
Categories: Cadence, EDA, Foundries, TSMC

IC designers contemplating the transition to 16nm FinFET technology for their next SoC need to be informed about design flow and IP changes, so TSMC teamed up with Cadence Design Systems today to present a webinar on that topic. I attended the webinar and will summarize my findings.

Shown below is a 3D layout concept of an ideal FinFET… Read More