Banner Electrical Verification The invisible bottleneck in IC design updated 1
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EDA

Electronic Design Automation

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Synopsys’s Next Generation Emulator, ZeBu Server-3

Synopsys’s Next Generation Emulator, ZeBu Server-3
by Paul McLellan on 02-28-2014 at 12:17 pm
Categories: EDA, Synopsys

Since Synopsys acquired Eve over a year ago, they haven’t announced anything new in the ZeBu product line. Emulators are not like software where you expect incremental releases a couple of times per year, each new “release” is a complete re-design using new hardware fabric in a new process technology. Earlier… Read More

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Mixed-Signal SoC Debugging & IP Integration Made Easy

Mixed-Signal SoC Debugging & IP Integration Made Easy
by Pawan Fangaria on 02-28-2014 at 7:30 am
Categories: Concept Engineering, EDA

A semiconductor SoC design can have multiple components at different levels of abstractions from different sources and in different languages. While designing an SoC, IPs at different levels have to be integrated without losing the overall design goals. Of course, quality of an IP inside and outside of an SoC must be tested thoroughly.… Read More

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IoT: the sum of all technology opportunities

IoT: the sum of all technology opportunities
by Don Dingee on 02-26-2014 at 5:00 pm
Categories: EDA

There was a time not that long ago, before smartphones arrived on the scene, where Mentor Embedded Nucleus RTOS was dominant in non-Nokia feature phones – Mentor is part of the “Billion Unit Mobile Club”. Since then, Mentor has been searching to recreate that type of success, and like so many other software firms, they are now aiming… Read More

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TI’s Way of Strategies – Formation & Execution

TI’s Way of Strategies – Formation & Execution
by Pawan Fangaria on 02-26-2014 at 8:30 am
Categories: EDA, Foundries, General

For a company to stand still and continually prosper even after facing several downturns in its career of 80+ years, and still move swiftly with strong commitment and confidence, its strategy has to be right and rock solid possessing sustainable competitive advantage, and of course it has to be an early mover in everything it does… Read More

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A Brief History of Chip Design at Apple Computer

A Brief History of Chip Design at Apple Computer
by Daniel Payne on 02-25-2014 at 9:36 pm
Categories: EDA

Steve Wozniak in 1976 designed the Apple 1 while working at HP during the daytime, and he used standard parts to keep costs low, like:

  • 6502 CPU from MOS Technology
  • 8K of DRAM
  • TTL logic for driving video and random logic
  • PROM to hold the BASIC language and primitive OS
… Read More
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SoC Functional Verification Planning and Management Goes Big

SoC Functional Verification Planning and Management Goes Big
by Daniel Payne on 02-24-2014 at 10:01 am
Categories: Cadence, EDA

Big SoC designs typically break existing EDA tools and old methodologies, which then give rise to new EDA tools and methodologies out of necessity. Such is the case with the daunting task of verification planning and management where terabytes of data have simply swamped older EDA tools, making them unpleasant and ineffective… Read More

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A Methodology for Assertion Reuse in SoC Designs

A Methodology for Assertion Reuse in SoC Designs
by Daniel Payne on 02-21-2014 at 4:24 pm
Categories: EDA

As your SoC design can contain hundreds of IP blocks, how do you verify that all of the IP blocks will still work together correctly once assembled? Well, you could run lots of functional verification at the full-chip level and hope for the best in terms of code coverage and expected behavior. You could buy an expensive emulator to … Read More

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6 reasons Synopsys covets C/C++ static analysis

6 reasons Synopsys covets C/C++ static analysis
by Don Dingee on 02-20-2014 at 5:00 pm
Categories: IP, Synopsys

By now, you’ve probably seen the news on Synopsys acquiring Coverity, and a few thoughts from our own Paul McLellan and Daniel Payne in commentary, who I respect deeply – and I’m guessing there are many like them out there in the EDA community scratching their heads a little or a lot at this. I’m not from corporate, but I am here… Read More

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Mounir Hahad Rejoins Silvaco

Mounir Hahad Rejoins Silvaco
by admin on 02-20-2014 at 4:16 pm
Categories: EDA

Mounir Hahad just joined Silvaco as VP engineering. And when I say joined I really mean rejoined. I had a call with him to find out how that happened.

Mounir studied in France for a PhD in computer science on numerical computing. In 1995 the then-director of TCAD at Silvaco called him up having read some of his published papers. Silvaco… Read More

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Before SPICE Circuit Simulation Comes TCAD Tools

Before SPICE Circuit Simulation Comes TCAD Tools
by Daniel Payne on 02-20-2014 at 3:19 pm
Categories: EDA

I’ve run SPICE circuit simulators since the 1970’s and they use transistor models where the device parameters are provided by the foundry. These transistor and interconnect parameters come from an engineer at the foundry who has characterized silicon with actual measurements or by running a TCAD (Technology CAD)… Read More