As design complexity and size is increasing, SoC verification has become one of the most difficult and time consuming tasks in the design closure.UVM (Universal Verification Methodology, an accellera initiative) is one of the best verification methodologies that support common language, coherent strategy, clarity and transparency… Read More
Electronic Design Automation
Chips Are Going 3D, DRC Needs to Go 3D Too
The last paradigm shift in DRC was around 0.35um when designs got too large to handle as flat data, and hierarchical approaches were required. Back then the design rules themselves were not that complex, the explosion of data volume came from the complexity of the design itself. But each process node added more design rules intricacies… Read More
Open Forum for Semiconductor Professionals!
The semiconductor industry has never been more exciting than it is today, at least not in my 30 years of experience. Things are moving faster than ever before making collaboration at all levels a requirement. At SemiWiki we are afforded the privilege of passes to semiconductor conferences around the world. We also have access to… Read More
Writing the unwritten rules with ALINT-PRO-CDC
EDA verification tools generally do a great job of analyzing the written rules in digital design. Clock domain crossings (CDCs) are more like those unwritten rules in baseball; whether or not you have a problem remains indefinite until later, when retaliation can come swiftly out of nowhere.
Rarely as overt or dramatic as a bench-clearing… Read More
A Public Synchronizer
You might ask yourself “Why would anyone want to have a public synchronizer available to download?” Usually designers just grab a flip-flop from his or her company’s or a standard cell vendor’s library. However, are these handy solutions the best course of action today? Current SoC designs have numerous clock domains providing… Read More
Integrated Spec Design & Documentation for SoC
One challenge in SoC projects is maintaining consistency between the specification, design and documentation throughout the product lifecycle. Imagine the chaos if your specification for power is 300 mW, the design is actually 350 mW and the documentation promises 250 mW. Traditionally the design and documentation process… Read More
Why Would You Leave Yahoo to Go Into EDA?
I sat down this afternoon with Peter Theunis, the CTO of Methodics. Conveniently their office is about a 15 minute walk from where I live so we could chat face to face.
Peter started programming when he was 8 and his first “product” was a weather system for orchards where sensors in the orchards would send information … Read More
Cadence 2014 Results
Cadence announced their Q4 and 2014 results yesterday. They are the only one of the big 3 EDA companies whose fiscal year is the calendar year so Synopsys and Mentor will not be joining them in announcing them this week.
I won’t go into the numbers in detail, you can find them all easily enough. But it is a pity that statements like… Read More
Concept: From Schematics to Debug
In the late 1990s I was the VP Engineering at Ambit Design Systems. We had a synthesis product (called BuildGates, nobody ever forgot the name). Both our own engineers and our customers wanted to be able to take a look at the gate-level netlist that was generated from their RTL. We used a product from a company called Concept Engineering… Read More
What’s Hot at SPIE Advanced Lithography
The 40[SUP]th[/SUP] SPIE Advanced Lithography conference will be at the San Jose Convention Center 22-26 February. Over the past few years, this conference has grown in scope to include emerging patterning technologies, like directed self-assembly (DSA) and design-process-technology co-optimization.
Underlying all … Read More
AI RTL Generation versus AI RTL Verification