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EDA

Electronic Design Automation

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Next Generation Formal Technology to Boost Verification

Next Generation Formal Technology to Boost Verification
by Pawan Fangaria on 06-08-2015 at 12:00 pm
Categories: Cadence, EDA

With growing complexities and sizes of SoCs, verification has become a key challenge for design closure. There isn’t a single methodology that can provide complete verification closure for an SoC. Moreover creation of verification environment including hardware, software, testbench and testcases requires significant … Read More

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Synopsys to Acquire Atrenta

Synopsys to Acquire Atrenta
by Paul McLellan on 06-07-2015 at 11:17 pm
Categories: EDA, Synopsys

I was at the DAC kickoff this evening in the Intercontinental Hotel. I was talking to Dave DeMaria, the senior marketing guy at Synopsys and he told me of a couple of minor press releases due to hit the wire tomorrow morning, didn’t sound important enough to be blogworthy. Aart was there too although I didn’t speak to him.… Read More

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ESD Protection Network Checking is Difficult But Necessary

ESD Protection Network Checking is Difficult But Necessary
by Tom Simon on 06-06-2015 at 6:00 pm
Categories: EDA, Magwel

I’ve written before about anti-fuse non-volatile memory, where the gate oxide is intentionally damaged in order to create a readable bit of data, but this is what most circuit designers never want to have happen to their logic gates. However, since the advent of MOS transistors the issue of Electrostatic Discharge (ESD) and the… Read More

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Vacationing with the Fabless Semiconductor Ecosystem!

Vacationing with the Fabless Semiconductor Ecosystem!
by Daniel Nenni on 06-05-2015 at 4:00 pm
Categories: EDA, Events, IP, Synopsys

The Design Automation Conference is the largest and most diverse event in the fabless semiconductor ecosystem. Next week in San Francisco you will see technology and people you have never seen before. You will benefit from the efforts of hundreds of thousands of semiconductor professionals like myself who have dedicated their… Read More

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Automate those voltage-dependent DRC checks!

Automate those voltage-dependent DRC checks!
by Beth Martin on 06-04-2015 at 10:00 pm
Categories: EDA, Siemens EDA

Because IC design and verification never gets simpler, verification engineers now have to comply with voltage-dependent DRC (VD-DRC) rules. What does this term mean, and what new challenges does it bring to the DRC task? I’d like to share what I learned during another water-cooler conversation with Dina Medhat, senior technical… Read More

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Is Avago Chip Industry’s Cisco?

Is Avago Chip Industry’s Cisco?
by Majeed Ahmad on 06-04-2015 at 3:00 pm
Categories: EDA

If Ford is a reference model for value chain in the Industrial Age, Cisco is the icon of the twenty-first-century digital economy. The networking gear maker, who achieved phenomenal growth with the rise of the Internet, has been remarkably successful in snapping up and integrating scores of companies for products it could not … Read More

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The Transistor is the Foundation of TCAD to Signoff

The Transistor is the Foundation of TCAD to Signoff
by admin on 06-04-2015 at 7:00 am
Categories: EDA, Silicon Photonics

At the most basic level, semiconductor design is all about transistors. Any report on a large microprocessor or mobile application processor is in awe about how many transistors it contains. Moore’s Law is all about the most economic way to manufacture transistors. Each process generation for the last decade and looking ahead… Read More

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MIPI Beyond Mobile, Semiwiki Blogger Paper at #52DAC!

MIPI Beyond Mobile, Semiwiki Blogger Paper at #52DAC!
by Daniel Nenni on 06-03-2015 at 10:00 am
Categories: EDA, IoT, IP

IoT or wearable: it’s fascinating to see how many articles, blogs, and comments have been posted about them during the last two years! IoT business potential is huge as are the number of possible applications. If we summarize the functions within a wearable system we can count:

[LIST=1]

  • CPU: it can be a standard Microcontroller
    • … Read More
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    Logic Synthesis Reborn

    Logic Synthesis Reborn
    by Daniel Payne on 06-03-2015 at 9:45 am
    Categories: Cadence, EDA

    Combine the pressures of Moore’s Law which enable billion transistor SoCs and the shortened time to market from consumer electronics product cycles and you have the perfect storm for EDA tool vendors. A modern SoC can have 500 or more blocks, creating both a design and verification challenge. How in the world do you write … Read More

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    Even More Integration and Automation for ARM-based Designs

    Even More Integration and Automation for ARM-based Designs
    by Daniel Payne on 06-03-2015 at 8:00 am
    Categories: Arm, EDA

    The attraction to an IP-based design methodology is that you can assemble an SoC from ready-made IP blocks, saving you valuable engineering development and verification time, while reducing risks from having to develop something from scratch and hoping that they meet industry standard specs. ARM is well known for supplying … Read More