Banner Electrical Verification The invisible bottleneck in IC design updated 1
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Latest Pinpoint Release Tackles DRC and Trend Lines

Latest Pinpoint Release Tackles DRC and Trend Lines
by Don Dingee on 07-06-2016 at 4:00 pm

After reading previous SemiWiki coverage on Dassault Systèmes and their ENOVIA Pinpoint solution, one big item seemed missing: how does this thing actually work? With all due respect to our other bloggers who covered when Dassault Systèmes acquired Pinpoint from Tuscany Design Automation, why Qualcomm is using Pinpoint, and… Read More


A Brief History of Platform Design Automation

A Brief History of Platform Design Automation
by Daniel Payne on 07-01-2016 at 12:00 pm

Two weeks ago I spoke on the phone with Albert Li, Founder and CEO of Platform DA about his EDA company. Prior to founding Platform DA in Beijing, Li worked at Accelicon which was acquired by Agilent in December 2011. Mr. Li graduated from Tsinghua University and Vanderbilt University, both in Electrical Engineering, and has written… Read More


Synopsys Launch EV6x Vision Processor… Challenging the Competition!

Synopsys Launch EV6x Vision Processor… Challenging the Competition!
by Eric Esteve on 06-30-2016 at 4:00 pm

When Synopsys bought Virage Logic in 2010, ARC processor IP was in the basket, but at that time ARC processor core was not the most powerful on the market, and by far. The launch of EV6x vision processor sounds like Synopsys has moved ARC processor core by several orders of magnitude in term of processing power. EV6x deliver up to 100X… Read More


From Zero to IoT Prototype in One Month

From Zero to IoT Prototype in One Month
by Bernard Murphy on 06-30-2016 at 7:00 am

The best things in life may not always be free, but they don’t have to be incredibly difficult to get to. A challenge for IoT designers has been that their bubbling excitement over the potential of their new gizmo is quickly tempered by the complexities of actually building the hardware. Not exactly what they have come to expect in … Read More


HBM controller IP holds the key to bandwidth

HBM controller IP holds the key to bandwidth
by Don Dingee on 06-29-2016 at 4:00 pm

We were waiting to see what a different roster including SK Hynix and Synopsys would have to say on HBM in the latest Open Silicon webinar. This event focused on HBM bandwidth issues; a packaging session on 2.5D interposers was promised for a future webinar.… Read More


Circuit Simulation Panel Discussion at #53DAC

Circuit Simulation Panel Discussion at #53DAC
by Daniel Payne on 06-29-2016 at 12:00 pm

Four panelists from big-name semiconductor design companies spoke about their circuit simulation experiences at #53DAC in Austin this year, so I attended to learn more about SPICE and Fast SPICE circuit simulation. I heard from the following four companies:… Read More


High Level Synthesis Update

High Level Synthesis Update
by Tom Dillinger on 06-29-2016 at 7:00 am

High-level synthesis (HLS) involves the generation of an RTL hardware model from a C/C++/SystemC description. The C code is typically referred to as abehavioraloralgorithmicmodel. The C language constructs and semantics available to architects enable efficient and concise coding – the code itself is smaller, easier to write/read,… Read More


It’s Time to Put Your Spice Netlists on a Diet

It’s Time to Put Your Spice Netlists on a Diet
by admin on 06-28-2016 at 7:00 am

Spice circuit simulation remains the backbone of IC design validation. Digital cell library developers rely upon Spice for circuit characterization, to provide the data for Liberty models. Memory IP designers utilize additional Spice features to perform statistical sampling. Analog and I/O interface designers extend these… Read More


Two New Announcements from Tanner EDA at #53DAC

Two New Announcements from Tanner EDA at #53DAC
by Daniel Payne on 06-27-2016 at 12:00 pm

Most mergers and acquisitions in the EDA world simply don’t work out financially a year or two after the deal is done, however I was pleasantly surprised to learn that Tanner EDA is doing quite well at #53DAC this year after the acquisition by Mentor Graphics back in March 2015. Everyone that I’ve been meeting with at … Read More


10 signs on the neural-net-based ADAS road

10 signs on the neural-net-based ADAS road
by Don Dingee on 06-24-2016 at 12:00 pm

Every day I read stuff about the coming of fully autonomous vehicles, and it’s not every day we get a technologist’s view of the hurdles faced in getting there. Chris Rowen, CTO of Cadence’s IP group, gave one of the best presentations I’ve seen on ADAS technology and convolutional neural networks (CNNs) at #53DAC, pointing… Read More