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Computer Vision and High-Level Synthesis

Computer Vision and High-Level Synthesis
by Daniel Payne on 03-15-2018 at 12:00 pm

Computer vision as a research topic has been around since the 1960’s and we are enjoying the benefits of this work in modern-day products all around us as robots with computer vision are performing an increasing number of tasks, even our farmers are using computer vision systems to become more productive:

  • AgEagle® has a drone
Read More

CEO Interview: Ramy Iskander of Intento Design

CEO Interview: Ramy Iskander of Intento Design
by Daniel Nenni on 03-14-2018 at 7:00 am

One of the more interesting parts of blogging for SemiWiki is getting to know emerging EDA and IP companies from around the world. As I have mentioned before, there are some incredibly intelligent people in the fabless semiconductor ecosystem solving very complex problems. It is a two way exchange of course since we know the market… Read More


Webinar Alert – Embedded Monitoring of Process and Voltage in SoCs

Webinar Alert – Embedded Monitoring of Process and Voltage in SoCs
by Daniel Payne on 03-13-2018 at 12:00 pm

In the old days to learn about new semiconductor IP you would have to schedule a sales call, listen to the pitch, then decide if the IP was promising or not. Today we have webinars which offer a lot less drama than a sales call, plus you get to ask your questions by typing away at the comfort of your desk, hopefully wearing headphones as … Read More


Another Application of Automated RTL Editing

Another Application of Automated RTL Editing
by Bernard Murphy on 03-13-2018 at 7:00 am

DeFacto and their STAR technology are already quite well known among those who want to procedurally apply edits to system-level RTL. I’m not talking here about the kind of edits you would make with your standard edit tools. Rather these are the more convoluted sort of changes you might attempt with Perl (or perhaps Python these days).… Read More


Clock Domain Crossing in FPGA

Clock Domain Crossing in FPGA
by Alex Tan on 03-12-2018 at 12:00 pm

Clock Domain Crossing (CDC) is a common occurrence in a multiple clock design. In the FPGA space, the number of interacting asynchronous clock domains has increased dramatically. It is normal to have not hundreds, but over a thousand clock domains interactions. Let’s assess why CDC is a lingering issue, what its impact and the … Read More


An OSAT Reference Flow for Complex System-in-Package Design

An OSAT Reference Flow for Complex System-in-Package Design
by Tom Dillinger on 03-09-2018 at 12:00 pm

With each new silicon process node, the complexity of SoC design rules and physical verification requirements increases significantly. The foundry and an EDA vendor collaborate to provide a “reference flow” – a set of EDA tools and process design kit (PDK) data that have been qualified for the new node. SoC design methodology … Read More


Don’t Stand Between The Anonymous Bug and Tape-Out (Part 1 of 2)

Don’t Stand Between The Anonymous Bug and Tape-Out (Part 1 of 2)
by Alex Tan on 03-09-2018 at 7:00 am

In the EDA space, nothing seems to be more fragmented in-term of solutions than in the Design Verification (DV) ecosystem. This was my apparent impression from attending the four panel sessions plus numerous paper presentations given during DVCon 2018 held in San Jose. Both key management and technical leads from DV users communityRead More


Is there anything in VLSI layout other than “pushing polygons”? (7)

Is there anything in VLSI layout other than “pushing polygons”? (7)
by Dan Clein on 03-08-2018 at 12:00 pm

The time is 1995 and my mandate as Layout Manager is to grow my team. I advertised everywhere but there were no experienced people in Canada that I can hire so the solution was back to training. I was the trainer a few times in Israel in MSIL but there we had a very organised material for layout, UNIX, software, etc. We had exercises, tests,… Read More


EDA and Semiconductor — Is There Growth In The Ecosystem?

EDA and Semiconductor — Is There Growth In The Ecosystem?
by Alex Tan on 03-07-2018 at 12:00 pm


The semiconductor industry has gone through several major transitions driven by different dynamics such as shift in business models (fab-centric to fab-less), product segmentation (system design house, IP developers) and end market applications (PC to cloud; and recently, to both automotive and Internet of Things — IOT’s,Read More


Students Should Attend DAC in SFO

Students Should Attend DAC in SFO
by Daniel Payne on 03-06-2018 at 12:00 pm

On LinkedIn I have some 2,116 connections and many of those are students looking to enter the field of EDA, IP or semiconductor design. What a wonderful opportunity these students have by attending the 55th annual DAC in San Francisco this summer from June 24-28. Technical sessions, keynote speeches, exhibitors, networking, … Read More