100X800 Banner (1)
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4360
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4360
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)

EDA CEO Outlook 2018 Partly Cloudy

EDA CEO Outlook 2018 Partly Cloudy
by Daniel Nenni on 04-16-2018 at 7:00 am

The funniest line of the EDA CEO Outlook event was that we should rename our Amazon Echos Wally. Yes Wally is that smart and he remembers pretty much everything. I wish I could rename my Echo Wally because my daughter in-law is named Alexa so we have to turn it off when she is over. The discussion took an interesting turn with EDA in the … Read More


Enabling A Data Driven Economy

Enabling A Data Driven Economy
by Alex Tan on 04-13-2018 at 12:00 pm


The theme of this year CDNLive Silicon Valley keynote given by Cadence CEO, Lip-Bu Tan evolves around data and how it drives Cadence to make a transition from System Design Enablement (SDE) to Data Driven Enablement (DDE). Before elaborating further, he noted on some CDNLive conference statistics: 120 sessions, 84% done by users,… Read More


HCM Is More Than Data Management

HCM Is More Than Data Management
by Alex Tan on 04-12-2018 at 12:00 pm

While tracking Moore’s Law has become a more expensive and difficult endeavor in the HPC design, the mobile SOC design space is also increasingly heterogeneous and complex. Strict safety guidelines such as the ISO-26262 being imposed in the automotive applications further exacerbate the situation.

Looking closer into the … Read More


Is there anything in VLSI layout other than “pushing polygons”? (8)

Is there anything in VLSI layout other than “pushing polygons”? (8)
by Dan Clein on 04-11-2018 at 12:00 pm

The year is 1999 and I decided that is time to try something else in layout. In 1989 in Israel I was part of the biggest chip in the world, the Motorola DSP9600. In 1998 in Canada I was part of the biggest Synchronous DRAM in the world, it was time to try analog/mixed signal/RF projects.

The opportunity came from PMC Sierra who already had… Read More


Embracing Architectural Intent

Embracing Architectural Intent
by Alex Tan on 04-10-2018 at 12:00 pm

During DVCon 2018 in San Jose, one topic widely covered was the necessity of describing and capturing intent. Defining our design intent up-front is crucial to the overall success of a design implementation. It is not limited to applying a process level intent, such as the use of verification intent with embedded assertions in … Read More


Emulation Outside the Box

Emulation Outside the Box
by Bernard Murphy on 04-10-2018 at 7:00 am

We all know the basic premise of emulation: hardware-assisted simulation running much faster than software-based simulation, with comparable accuracy for cycle-based 0/1 modeling, decently fast setup, and comparably fine-grained debug support. Pretty obvious value for running big jobs with long tests. But emulators tend… Read More


EDA CEO Outlook 2018

EDA CEO Outlook 2018
by Daniel Nenni on 04-06-2018 at 12:00 pm

The EDA CEO outlook took an interesting turn last night but before I get into that I will offer a few comments about the start of the show. I attend this event every year for the content but also for the networking. It isn’t everyday you get to hang out with semiconductor industry elite and have candid conversations over food and drinks.… Read More


The 4th Way Beyond Simulation, FPGA Synthesis, and Emulation

The 4th Way Beyond Simulation, FPGA Synthesis, and Emulation
by Camille Kokozaki on 04-06-2018 at 7:00 am

As verification continues to be a key ingredient in successful design implementation, new approaches have been tried to balance cost, time to results and comprehensive analysis in designs that require large patterns in some application like Image Processing. Simulation environments are well proven, and designers tend to … Read More


Stress and Aging

Stress and Aging
by Bernard Murphy on 04-05-2018 at 12:00 pm

These failings aren’t just a cross we humans bear; they’re also a concern for chips, particularly in electrical over-stress (EOS) and aging of the circuitry. Such concerns are not new, but they are taking on new urgency given the high reliability and long lifetime expectations we have for safety-critical components in cars and… Read More


Mentor Leads Emulation Innovation

Mentor Leads Emulation Innovation
by Daniel Nenni on 04-05-2018 at 8:00 am

Publishing eBooks on FPGA Prototyping and Emulation really was an eye opener for me as a long time EDA and IP professional. Both markets are considered EDA in the traditional sense but they are very much in the systems business with a lot of IP. Both markets are also growing very rapidly and operate side-by-side with complimentary… Read More