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Design Technology CoOptimization at SPIE 2020

Design Technology CoOptimization at SPIE 2020
by Daniel Nenni on 02-14-2020 at 6:00 am

DTCO Fig1 SPIE2020 Semiwiki

SLiC Library tool dramatically accelerates DTCO for 3nm and beyond

In advanced technology nodes below 10nm, Design and Process Technology development have become increasingly intertwined. In older nodes the traditional technology roll-out was done mostly in a sequential manner with clear geometry scaling targets set by … Read More


Thermal Reliability Challenges in Automotive and Data Center Applications – A Xilinx Perspective

Thermal Reliability Challenges in Automotive and Data Center Applications – A Xilinx Perspective
by Bernard Murphy on 02-13-2020 at 6:00 am

thermometer

I wrote recently on ANSYS and TSMC’s joint work on thermal reliability workflows, as these become much more important in advanced processes and packaging. Xilinx provided their own perspective on thermal reliability analysis for their unquestionably large systems – SoC, memory, SERDES and high-speed I/O – stacked within a … Read More


De-Risking High-Speed RF Designs from Electromagnetic Crosstalk Issue

De-Risking High-Speed RF Designs from Electromagnetic Crosstalk Issue
by Mike Gianfagna on 02-12-2020 at 6:00 am

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At DesignCon 2020, ANSYS sponsored a series of very high-quality presentations.  Some focused on advanced methods and new technology exploration and some provided head-on, practical and actionable capabilities to improve advanced designs. The presentation I will discuss here falls into the latter category. The topic was… Read More


Innovation in Verification – February 2020

Innovation in Verification – February 2020
by Bernard Murphy on 02-11-2020 at 6:00 am

Innovation in Verification

This blog is the next in a series in which Paul Cunningham (GM of the Verification Group at Cadence), Jim Hogan and I pick a paper on a novel idea in verification and debate its strengths and opportunities for improvement.

Our goal is to support and appreciate further innovation in this area. Please let us know what you think and please… Read More


Emerging Requirements for Electromagnetic Crosstalk Analysis

Emerging Requirements for Electromagnetic Crosstalk Analysis
by Tom Dillinger on 02-10-2020 at 10:00 am

EM coupling wire segments

This article will describe the motivations for pursuing a new flow in the SoC design methodology.  This flow involves the extraction, evaluation, and analysis of a full electromagnetic coupling model for a complex SoC and its package environment.  The results of this analysis highlight the impact of electromagnetic coupling… Read More


It’s The Small Stuff That Gets You …

It’s The Small Stuff That Gets You …
by Mike Gianfagna on 02-10-2020 at 6:00 am

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The last session I attended at DesignCon 2020 wasn’t a session at all. Rather it was an interactive discussion with Todd Westerhoff, product manager for electronic board systems at Mentor Graphics. Todd made some observations about the way high-performance PCBs are designed today and perhaps the way they should be designed. … Read More


AI Interposer Power Modeling and HBM Power Noise Prediction Studies

AI Interposer Power Modeling and HBM Power Noise Prediction Studies
by Mike Gianfagna on 02-07-2020 at 6:00 am

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I attended a session on 2.5D silicon interposer analysis at DesignCon 2020. Like many presentations at this show, ecosystem collaboration was a focus. In this session, Jinsong Hu (principal application engineer at Cadence) and Yongsong He (senior staff engineer at Enflame Tech) presented approaches for interposer power modeling… Read More


Executive Interview: Howie Bernstein of HCL

Executive Interview: Howie Bernstein of HCL
by Daniel Nenni on 02-06-2020 at 6:00 am

Howie Bernstein SemiWiki

Howie began his career at Digital Equipment Corporation working on real-time device drivers, but within a few years started working at the other end of the stack with one of the pioneering electronic mail systems.  Since then, Howie has worked on developing systems involving electronic mail, workflow processing, configuration… Read More


Verification, RISC-V and Extensibility

Verification, RISC-V and Extensibility
by Bernard Murphy on 02-05-2020 at 6:00 am

RISC-V

RISC-V is obviously making progress. Independent of licensee signups and new technical offerings, the simple fact that Arm is responding – in fundamental changes to their licensing model and in allowing custom user extensions to the instruction set – is proof enough that they see a real competitive threat from RISC-V.

Which all… Read More


Signal Channel Design and Simulation for Silicon Interposer Packaging on High-Speed SerDes

Signal Channel Design and Simulation for Silicon Interposer Packaging on High-Speed SerDes
by Mike Gianfagna on 02-04-2020 at 10:00 am

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This year is the 25th anniversary for DesignCon.  The show has changed a lot over the years. Today, it’s a vibrant showcase of all aspects of advanced product design – from ICs to boards to systems. The show floor reflects the diverse ecosystem. If you missed it this year, definitely plan to go next year.

The DesignCon technical program… Read More