Signal Integrity (SI) and Power Integrity (PI) issues are critical to analyze, ensuring the proper operation of PCB systems and IC packages, yet the computational demands from EDA tools can cause engineers to only analyze what they deem are critical signals, instead of the entire system. Cadence has managed to overcome this SI/PI… Read More
Advanced Audio Tightens Integration to Implementation
You might think that in the sensing world all the action is in imaging and audio is a backwater. While imaging features continue to evolve, audio innovations may be accelerating even faster to serve multiple emerging demands: active noise cancellation, projecting a sound stage from multiple speakers, 3D audio and ambisonics,… Read More
Hearing Aids are Embracing Tech, and Cool
You could be forgiven for thinking of hearing aids as the low end of tech, targeted to a relatively small and elderly audience. Commercials seem unaware of advances in mobile consumer audio, and white-haired actors reinforce the intended audience. On the other hand, the World Health Organization has determined that at least 6%… Read More
Safety Grading in DNNs. Innovation in Verification
How do you measure safety for a DNN? There is no obvious way to screen for a subset of safety-critical nodes in the systolic array at the heart of DNNs. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas.… Read More
Bird’s Eye View Magic: Cadence Tensilica Product Group Pulls Back the Curtain
Even for experienced technologists some technologies can seem almost indistinguishable from magic. One example is the bird’s eye camera view available on your car’s infotainment screen. This view appears to be taken from a camera hovering tens of feet above your car. As an aid to parallel parking, it’s a brilliant invention; … Read More
Intel and Cadence Collaborate to Advance the All-Important UCIe Standard
The Universal Chiplet Interconnect Express™ (UCIe™) 1.0 specification was announced in early 2022 and a UCIe 1.1 update was released on August 8, 2023. This open standard facilitates the heterogeneous integration of die-to-die link interconnects within the same package. This is a fancy way of saying the standard opens the door… Read More
Bug Hunting in NoCs. Innovation in Verification
Despite NoCs being finely tuned in legacy subsystems, when subsystems are connected in larger designs or even across multi-die structures, differing traffic policies and system-level delays between NoCs can introduce new opportunities for deadlocks, livelocks and other hazards. Paul Cunningham (GM, Verification at Cadence),… Read More
Overcoming Verification Challenges of SPI NAND Flash Octal DDR
As the automotive industry continues to evolve, the demands for high-capacity, high-speed storage solutions are intensifying. Autonomous vehicles and V2X (Vehicle-to-Everything) communication systems generate and process massive amounts of data, necessitating advanced storage technologies capable of meeting these… Read More
The Impact of UCIe on Chiplet Design: Lowering Barriers and Driving Innovation
The semiconductor industry is experiencing a significant transformation with the advent of chiplet design, a modular approach that breaks down complex chips into smaller, functional blocks called chiplets. A chiplet-based design approach offers numerous advantages, such as improved performance, reduced development … Read More
The Future of Logic Equivalence Checking
Logic equivalence checking (LEC) is an automated process to verify that modified versions of a design evolving through implementation remain logically equivalent to the functionally signed-off RTL. This becomes important when accounting for retiming optimizations and for necessary implementation-stage ECOs which must… Read More