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Semiconductor Ecosystem Keynotes: ARM 2012

Semiconductor Ecosystem Keynotes: ARM 2012
by Daniel Nenni on 05-17-2012 at 5:00 pm

Yesterday’s SEMICO IP Ecosystem Conference was well worth the time. Everybody was there: ARM, Synopsys, Cadence, Mentor Graphics, GlobalFoundries, TSMC, MIPS, Tensilica, AMD, Atrenta, Sonics, and Tabula, everybody except Intel of course. What do Intel and I have in common? We don’t play well with others…

First up was… Read More


Cadence Update 2012!

Cadence Update 2012!
by Daniel Nenni on 05-14-2012 at 9:00 pm

What’s new at Cadence? Quite a bit actually. I have always been a Cadence fan, I mean really, they gave birth to modern EDA. Unfortunately, Cadence really lost me during the Avant! legal action, the Mike Fister years, and EDA360. Recently, however, Cadence has made some big changes that will definitely get them back on my good side.… Read More


28nm Layout Needs Signoff Quality at Design Time

28nm Layout Needs Signoff Quality at Design Time
by Pawan Fangaria on 05-03-2012 at 8:30 pm

We are all aware that at 28nm and below several types of complex layout effects manifest themselves into the design and pose a herculean task, with several re-spins to correct them at pre-tapeout. It’s apparent that the layout needs to be correct by construction at the very beginning during the design stage.

Having worked at CadenceRead More


GSA 3DIC and Cadence

GSA 3DIC and Cadence
by Paul McLellan on 04-29-2012 at 10:00 pm

At the GSA 3D IC working group meeting, Cadence presented their perspective on 3D ICs. Their view will turn out to be important since the new chair of the 3D IC working group is going to be Ken Potts of Cadence. Once GSA decided the position could not be funded then an independent consultant like Herb Reiter had to bow out and the position… Read More


Kadenz Leben: CDNLive! EMEA

Kadenz Leben: CDNLive! EMEA
by Paul McLellan on 04-27-2012 at 2:01 am

If you are in Europe then the CDNLive! EMEA user conference is in Munich at the Dolce Hotel from May 14th to 16th. Like last month’s CDNLive! in Cadence’s hometown San Jose, the conference focuses on sharing fresh ideas and best practices for all aspects of semiconductor design from embedded software down to bare silicon.… Read More


Cadence support for the Open NAND Flash Interface (ONFI) 3.0 controller and PHY IP solution + PCIe Controller IP opening the door for NVM Express support

Cadence support for the Open NAND Flash Interface (ONFI) 3.0 controller and PHY IP solution + PCIe Controller IP opening the door for NVM Express support
by Eric Esteve on 04-11-2012 at 10:19 am

The press release about ONFI 3.0 support was launched by Cadence at the beginning of this year. It was a good illustration of Denali, then Cadence, long term commitment to Nand Flash Controller IP support. The ONFI 3 specification simplifies the design of high-performance computing platforms, such as solid state drives and enterprise… Read More


Analog Automation – Needs Design Perspective

Analog Automation – Needs Design Perspective
by Pawan Fangaria on 04-11-2012 at 7:00 am

Recently I was researching the keynote speeches of isQED (International Society for Quality Electronic Design) Symposium 2012 and saw the very first, great presentation, “Taming the Challenges in Advanced Node Design” by Tom Beckley, Sr. VP at Cadence. I know Tom very well as I have worked with him and I admire his knowledge, authority… Read More


Singapore honors Lip-Bu Tan

Singapore honors Lip-Bu Tan
by Paul McLellan on 03-25-2012 at 11:08 pm

Lip-Bu Tan, the CEO of Cadence, has been named by the Singapore Business Awards as Outstanding CEO (overseas) last week. These awards were launched in 1985 by the Business Times and DHL, so this year is the 27th year of the award, created to recognize business leaders in Singapore and abroad.

As it happens, Cadence flew me first class… Read More


According with Cadence, PCI Express gen-3, to be the PCIe solution for the mainstream market as soon as in 2012

According with Cadence, PCI Express gen-3, to be the PCIe solution for the mainstream market as soon as in 2012
by Eric Esteve on 03-21-2012 at 9:10 am

The launch from Cadence of the PCI Express 3.0 Controller IP was officially done about one year ago, and demonstrated at the June 2011 PCI-SIG Developer’s Conference, where Cadence Design IP for PCI Express 3.0 controller IP implemented as a high-performance, dual-mode, 128-bit data-path, x8 PCI Express 3.0 controller… Read More