You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please,
join our community today!
WP_Term Object
(
[term_id] => 15
[name] => Cadence
[slug] => cadence
[term_group] => 0
[term_taxonomy_id] => 15
[taxonomy] => category
[description] =>
[parent] => 157
[count] => 621
[filter] => raw
[cat_ID] => 15
[category_count] => 621
[category_description] =>
[cat_name] => Cadence
[category_nicename] => cadence
[category_parent] => 157
[is_post] =>
)
WP_Term Object
(
[term_id] => 15
[name] => Cadence
[slug] => cadence
[term_group] => 0
[term_taxonomy_id] => 15
[taxonomy] => category
[description] =>
[parent] => 157
[count] => 621
[filter] => raw
[cat_ID] => 15
[category_count] => 621
[category_description] =>
[cat_name] => Cadence
[category_nicename] => cadence
[category_parent] => 157
[is_post] =>
)
Successful projects leverage the investment in comprehensive methodology and resource planning, covering design and analysis flows – that planning effort is especially important for functional verification.
The emergence of complex SoC designs for advanced automotive applications has led to a major focus on verification… Read More
It seems that it has always been that there were packages and ICs, and in the design tool world “never the twain shall meet”. The tools for designing packages were completely separate from the tools used to design IC’s. This was so profoundly true that even after Cadence merged with Valid Logic back in the early 90’s, their Allegro … Read More
At the November 14 Cadence Automotive Summit, Ian Dennison, Senior Group Director, outlined sensor enablement technologies and SoC mixed-signal design solutions, from Virtuoso electrically aware design with high current, high reliability, yield and performance tools and methodologies enabling ADAS/AV sensors for vehicle… Read More
As a preferred carrier to data or energy, photonics technology is becoming broad and diverse. In IC design, silicon-photonics technology has been the enabler of new capabilities and has revolutionized many applications as Moore’s-based scaling started to experience a slowdown. It acts as new on-chip inductor in HPC design … Read More
Cadence held a well-attended Automotive Summit where Cadence presented an overview of their solution and system enablement along with industry experts and established or startup companies sharing their perspective and product features from autonomous driving, LiDAR, Radar, thermal imaging, sensor imaging, and AI.… Read More
At a superficial level, emulation in the hardware design world is just a way to run a simulation faster. The design to be tested runs on the emulator, connected to whatever test mechanisms you desire, and the whole setup can run many orders of magnitude faster than it could if the design was running inside a software simulator. And … Read More
Ambiq Micro has built a family of voice processing MCU dedicated to battery powered, energy sensitive systems, supporting mobile application like wearable. The company is facing two strong challenges: support computationally intensive processing (NN-based far field) and speech recognition algorithms, while offering … Read More
Cadence has done a good job of keeping up with the needs of analog RF designs. Of course, the term RF used to be reserved for a thin slice of designs that were used specifically in RF applications. Now, it covers things like SerDes for networking chips that have to operate in the gigahertz range. Add that to the trend of combining RF and… Read More
IBIS-AMI Model Generation Simplifiedby Tom Dillinger on 10-25-2018 at 12:00 pmCategories: Cadence, EDA
The increasing demand for data communication throughput between system components has driven the requirement for faster SerDes IP data rates. The complexity of the transmit (Tx) and receive (Rx) signal conditioning functions has correspondingly evolved. As a result, the simulation methodology for SerDes electrical interface… Read More
The Cadence Tensilica DNA100 DSP IP core is not a one-size-fits-all device. But it’s highly modular in order to support AI processing at the edge, delivering from 0.5 TMAC for on-device IoT up to 10s or 100 TMACs to support autonomous vehicle (ADAS). If you remember the first talks about IoT and Cloud, a couple of years ago, the IoT … Read More