Author: Tom Simon

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Calibre Can Calculate Chip Yields Correlated to Compromised SRAM Cells

Calibre Can Calculate Chip Yields Correlated to Compromised SRAM Cells
by Tom Simon on 04-11-2017 at 12:00 pm
Categories: EDA, Siemens EDA

It seems like I have written a lot about SRAM lately. Let’s face it SRAM is important – it often represents large percentages of the area on SOC’s. As such, SRAM yield plays a major role in determining overall chip yields. SRAM is vulnerable to defect related failures, which unlike variation effects are not Gaussian in nature. Fabrication… Read More

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When Once is Not Enough, But Unlimited is Too Much

When Once is Not Enough, But Unlimited is Too Much
by Tom Simon on 04-04-2017 at 12:00 pm
Categories: IP, Sidense

When people think about non volatile memory, the first thing that usually comes to mind is NAND flash like that used in SSD’s or in microcontrollers to hold on-board code. Of course, there is also EEPROM and other types of NVM as well that can be used to hold data and code for the multitude of connected devices that are so common now. For… Read More

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When is "off" not really off?

When is "off" not really off?
by Tom Simon on 03-29-2017 at 12:00 pm
Categories: Dolphin Design, Events, IP, Mobile

With the old fashioned on-off power switch came certainty of power consumption levels. This was fine back in the days before processor controlled appliances and devices. On was on and off was off: full current or no current. With the first personal computers you always had to wait for the boot process to complete before you could … Read More

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Who knew designing PLL’s was so complicated?

Who knew designing PLL’s was so complicated?
by Tom Simon on 03-27-2017 at 12:00 pm
Categories: Events, IP, Silicon Creations

Well it comes as no surprise to those that use and design them, that PLL’s are a world unto themselves and very complicated indeed. With PLL’s we are talking about analog designs that rely on ring oscillators or LC tanks. They are needed on legacy nodes, like the ones that IoT chips are based on, and they are crucial for high speed advanced… Read More

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SRAM Optimization Saves Power on SOC’s and in Systems

SRAM Optimization Saves Power on SOC’s and in Systems
by Tom Simon on 03-21-2017 at 12:00 pm
Categories: EDA, Magwel

Mobile device designers face the dilemma of reducing power and at the same time maintaining or increasing performance. Consumers will not tolerate increased battery life at the expense of performance. If it were otherwise, designers could simply dial back clock rates. Without this simple cure, the best way to reduce power for… Read More

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Unlocking Access to SOC’s for IoT Edge Product Developers

Unlocking Access to SOC’s for IoT Edge Product Developers
by Tom Simon on 03-13-2017 at 4:00 pm
Categories: EDA, IoT, Siemens EDA

In the wake of the many mega mergers and consolidation in the semiconductor and electronics space, it is easy to say that opportunities for smaller companies are shrinking. Indeed, quite the opposite might be true. The larger companies, like Broadcom, ARM, Qualcomm, Analog Devices, Microchip, Maxim and Infineon (to name a few)… Read More

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Improved Timing Closure for Network-on-Chip based SOC’s

Improved Timing Closure for Network-on-Chip based SOC’s
by Tom Simon on 03-09-2017 at 12:00 pm
Categories: Arteris, IP

Network on chip (NoC) already has a long list of compelling reasons driving its use in large SOC designs. However, this week Arteris introduced their PIANO 2.0 software that provides an even more compelling reason to use their FlexNoC architecture. Let’s recap. Arteris FlexNoC gives SOC architects and designers a powerful tool… Read More

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On-Chip Power Distribution Networks Get Help from Magwel’s RNi

On-Chip Power Distribution Networks Get Help from Magwel’s RNi
by Tom Simon on 02-02-2017 at 12:00 pm
Categories: EDA, Magwel

Counting squares is a useful tool for calculating simple resistance in wires, but falls short in reality when wires deviate from ideal. Frequently the use of RC extraction tools for determining resistance in signal lines in digital designs can be effective and straightforward. However, there are classes of nets in designs that… Read More

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Timing Closure Complexity Mounts at FinFET Nodes

Timing Closure Complexity Mounts at FinFET Nodes
by Tom Simon on 01-27-2017 at 7:00 am
Categories: Arteris, EDA, FinFET, IP

Timing closure is the perennial issue in digital IC design. While the specific problem that has needed to be solved to achieve timing closure over the decades has continuously changed, it has always been a looming problem. And the timing closure problem has gotten more severe with 16/14nm FinFET SoCs due to greater distances between… Read More

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Intel Conveys Compute Card Capabilities at CES

Intel Conveys Compute Card Capabilities at CES
by Tom Simon on 01-16-2017 at 12:00 pm
Categories: Intel Foundry, IoT

Intel is once again adding a new computing form factor to the mix. At CES Intel announced its new Intel Compute Card. It combines CPU, GPU, DRAM, storage, WiFi, and communications inside a small modular housing slightly larger than a credit card and about 5mm thick. Intel already offers its Compute Stick, but it is limited in its interface… Read More