My recent article, ‘Chip War without Soldiers’ explained the importance of upskilling and preparing the chip design workforce in this current scenario, and it also explained how it will lead to ‘Fabs without Chips’ if we don’t prioritize it. VLSI Engineers are the pillars of the semiconductor industry, and they can only transform… Read More
Author: Sivakumar PR
Upskill Your Smart Soldiers and Conquer the Chip War in Style!
Chip War without Soldiers
Every country realizes the importance of producing skilled chip designers who could decide their success as soldiers by creating advanced AI chips for winning the Chip War. Also, every country is now gearing up to build a good semiconductor manufacturing ecosystem to balance the global semiconductor supply chain that could … Read More
Maven Silicon’s RISC-V Processor IP Verification Flow
RISC-V is a general-purpose license-free open Instruction Set Architecture [ISA] with multiple extensions. It is an ISA separated into a small base integer ISA, usable as a base for customized accelerators and optional standard extensions to support general-purpose software development. RISC-V supports both 32-bit and … Read More
Is your career at RISK without RISC-V?
I am delighted to share my technical insights into RISC-V in this article to inspire and prepare the next generation of chip designers for the future of the open era of computing. If you understand how we build complex electronic devices like desktops and smartphones using processors, you would be more interested in learning and… Read More
SoC Verification Flow and Methodologies
We need more and more complex chips and SoCs for all new applications that use the latest technologies like AI. For example, Apple’s 5nm SoC A14 features 6-core CPU, 4 core-GPU and 16-core neural engine capable of 11 trillion operations per second, which incorporates 11.8 billion transistors, and AWS 7nm 64-bit Graviton2 custom… Read More
Verification IP vs Testbench
Anyone can create a testbench[TB] and verify the design, but it can’t be simply reused as a verification IP [VIP]. So I would like to address in this article: What is VIP? How can we build a high-quality VIP? How can we verify the VIP? What else can we do to make the VIP unique and commercially more valuable?
Most of the module/IP level … Read More
Facing the Quantum Nature of EUV Lithography