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Oasys announced that it closed its series B funding round with investments from Intel Capital and Xilinx. The fact that any EDA company has closed a funding round is newsworthy these days; companies running out of cash and closing the doors seems to be a more common story.
Oasys has been relatively quiet, which some people have taken… Read More
EDPS: SoC FPGAsby Paul McLellan on 04-09-2012 at 4:00 amCategories: Events, FPGA
Mike Hutton of Altera spends most of his time thinking about a couple of process generations out. So a lot of what he worries about is not so much the fine-grained architecture of what they put on silicon, but rather how the user is going to get their system implemented. 2014 is predicted to be the year in which over half of all FPGAs will… Read More
EDPS: Parallel EDAby Paul McLellan on 04-08-2012 at 10:00 pmCategories: EDA, Events
EDPS was last Thursday and Friday in Monterey. I think that this is a conference that more people would benefit from attending. Unlike some other conferences, it is almost entirely focused around user problems rather than doing a deep dive into things of limited interest. Most of the presentations are more like survey papers and… Read More
Analyzing the operation of a modern SoC, especially analyzing its power distribution network (PDN) is getting more and more complex. Today’s SoCs no longer operate on a continuous basis, instead functional blocks on the IC are only powered up to execute the operation that is required and then they go into a standby mode, … Read More
DAC Pavilion Panelsby Paul McLellan on 04-05-2012 at 12:00 amCategories: EDA, Events
Once again DAC has a full program of panel sessions that take place on the exhibit floor at the DAC pavilion, aka booth 310.
Gary Smith kicks off the program with his annual “What’s Hot at DAC” presentation on Monday, June 4th, from 9:15-10:15am. The rest of Monday’s pavilion panels are:
- “Low power to the people,” a panel discussing
…
Read More
Mentor’s U2U user group meeting in Santa Clara is next week on April 12th at the Santa Clara Marriott. For those of you on the east coast the Waltham U2U is on May 16th, and for Europeans the Munich U2U will be on October 25th. Registration is open for both Santa Clara and Waltham, and there is a call for papers for Munich.
The day … Read More
Jasper Asian Seminarsby Paul McLellan on 04-04-2012 at 1:38 amCategories: EDA
Jasper has three seminars coming up in May in Hsinchu (Taiwan), Beijing and Shanghai. These are full-day seminars on how to solve critical verification challenges using state-of-the-art formal technology. Breakfast and lunch will be served.
This full-day tutorial will be given by technical experts for verification experts… Read More
You have probably heard something about ARM’s big.LITTLE architecture. This links a Cortex-A15 multi-core CPU with a Cortex-A7 CPU. The A15 is a high-performance processor and the A7 is a very low power processor. The basic idea is that when high-performance is required (playing a graphical video game on your smartphone,… Read More
Part I (here) looked at a bit of the history of scripting, makefiles and other approaches to more formally specify and institutionalize EDA design flows.
The most sophisticated tool I know that looks at this issue is RTDA’s FlowTracer.… Read More
The Art of Flows, Part Iby Paul McLellan on 03-29-2012 at 1:00 amCategories: EDA
These days, the flows that are used to build semiconductor designs are rightly regarded as part of the intellectual property of the company that developed and used them.
But it didn’t always used to be that way.… Read More
TSMC N3 Process Technology Wiki