Moore’s Law has been about device density, specifically transistor density, increasing every certain number of years. Although cost is the most easily grasped advantage, there are two other benefits: higher performance (speed) and reduced power. When these benefits are compromised, they can also pose a scaling limitation.
Author: Fred Chen
Contact Resistance: The Silent Device Scaling Barrier
The Uncertain Phase Shifts of EUV Masks
EUV (Extreme UltraViolet) lithography has received attention within the semiconductor industry since its development inception in 1997 with the formation of the EUV LLC [1], and more recently, since the 7nm node began, with limited use by Samsung and TSMC being touted as key advantages [2, 3]. As with any key critical technology,
MOSFET Gate Length Scaling Limit at Reduced Threshold Voltages
As transistor dimensions shrink to follow Moore’s Law, the functionality of the gate used to switch on or off the current is actually being degraded by the short channel effect (SCE) [1-5]. Moreover, the simultaneous reduction of voltage aggravates the degradation, as will be discussed below.
A Practical Lower Limit of… Read More
Reliable Line Cutting for Spacer-based Patterning
Spacer-defined patterning is an expected requirement for advanced semiconductor patterning nodes with feature sizes of 25 nm or less. As the required gaps between features go well below the lithography tool’s resolution limit, the use of cut exposures to separate features is used more often, especially in chips produced… Read More
Lithography Resolution Limits: Line End Gaps
In a previous article [1], the Rayleigh criterion was mentioned as the resolution limit for the distance between two features. On the other hand, in a following article [2], the minimum pitch was mentioned for the resolution limit for arrayed features. In this article, we reconcile the two by considering gaps between arrayed features,… Read More
Lithography Resolution Limits – Arrayed Features
State-of-the-art chips will always include some portions which are memory arrays, which also happen to be the densest portions of the chip. Arrayed features are the main targets for lithography evaluation, as the feature pitch is well-defined, and is directly linked to the cost scaling (more features per wafer) from generation… Read More
Lithography Resolution Limits: Paired Features
As any semiconductor process advances to the next generation or “node”, a sticky point is how to achieve the required higher resolution. As noted in another article [1], multipatterning (the required use of repeated patterning steps for a particular feature) has been practiced already for many years, and many have… Read More
Low Energy Electrons Set the Limits for EUV Lithography
EUV lithography is widely perceived to be the obvious choice to replace DUV lithography due to the shorter wavelength(s) used. However, there’s a devil in the details, or a catch if you will.
Electrons have the last word
The resist exposure is completed by the release of electrons following the absorption of the EUV photon.… Read More
The Need for Low Pupil Fill in EUV Lithography
Extreme ultraviolet (EUV) lithography targets sub-20 nm resolution using a wavelength range of ~13.3-13.7 nm (with some light including DUV outside this band as well) and a reflective ring-field optics system. ASML has been refining the EUV tool platform, starting with the NXE:3300B, the very first platform with a numerical
A Forbidden Pitch Combination at Advanced Lithography Nodes
The current leading edge of advanced lithography nodes (e.g., “7nm” or “1Z nm”) features pitches (center-center distances between lines) in the range of 30-40 nm. Whether EUV (13.5 nm wavelength) or ArF (193 nm wavelength) lithography is used, one thing for certain is that the minimum imaged pitch … Read More
IEDM 2025 – TSMC 2nm Process Disclosure – How Does it Measure Up?